vi Application Note
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design
Figures1 IP over ATM Encapsulation Format ............................................................. .........9
2 Frame and PDU Length vs. IP Packet Length ............................................. .......10
3 Expected Ethernet Transmit Bandwidth .............................................................. 11
4 Developer’s Workbench - ATM Data Stream Dialog Box......... ...........................12
5 Developer’s Workbench - IX Bus Device Status Window ..................... ..............13
6 System Programming Model.............. ................................................................. 14
7 IXP1240 1xATM OC-12 and 8xEthernet 100Mbps Microengin e Partitioning...... 15
8 IXP1240 OC-3 4xATM and 8xEthernet 100Mbps Microengine Partitioning........ 16
9 IXP1200 2xATM OC-3 Software-CRC and 4xEthernet 100Mbps Microengine Par-
titioning........................................ ........................................................................ 17
10 ATM to Ethernet Processing Steps ..................................................................... 18
11 Ethernet to ATM Processing Steps ..................................................................... 19
12 ATM Receive High Level Algorithm ............................ ........................................ 21
13 ATM Transmit High Level Algorithm ........................... ........................................ 22
14 IP Router High Level Algorithm................ ........................................................... 23
15 Ethernet Receive High Level Algorithm ................ .............................................. 24
16 First Cell of a PDU in RFIFO and in DRAM .................................... ....................26
17 Two-Cell PDU in DRAM ...................................................................................... 26
18 Transmit cell as seen in DRAM.......... ................................................................. 27
19 Transmit cell seen in TFIFO............................................... ...... ....... ...... ....... ...... . 27
20 CRC-32 High Level Algorithm ............................................................................. 29
21 Hashed VC Table Structure .................................................................. ..............31
22 VC Table Index ..................................................... ..............................................32
23 VC Lookup Entry Table (VC_TABLE_HASHED) ......................................... .......32
24 VC Lookup Table Entry (VC_TABLE_LINEAR) ................................................. .33
25 IP Route Table Entry - ATM Destination ............................................................. 38
26 IP Route Table Entry - Ethernet Destination ....................................................... 38
27 SRAM Descriptor to DRAM Buffer Mapping ............... ........................................ 39
28 Buffer Descriptor Format for ATM Transmit Destination Port .. ...........................39
29 Buffer Descriptor Format for Ethernet Transmit Destination Port .......................40
30 DRAM Data Buffer Format - 12 Byte Offset (Received by ATM) .......... ..............40
31 DRAM Data Buffer Format - 6 Byte Offset (Received by ATM, Transmi tted by
Ethernet) ............................................................................................... ..............40
32 DRAM Data Buffer Format - 6 Byte Offset (Recei ved by Ethernet, Transmitted by
ATM) ..................................................................................................... ..............40
33 DRAM Data Buffer Received by Ethernet ........................................................... 40
34 Buffer Descriptor Queue API....................................... ........................................46
35 Buffer Descriptor Queue Descriptor Structure (Resides in SRAM) ..................... 46
36 Buffer Descriptor Queue Structure (Only Relevant Part Shown) .......... ..............46
37 Illustration of Array of 32-bit Words.... ................................................................. 57
38 Illustration of Byte Sequence ................................ .............................................. 57
39 Definitions ....................................................................................... ....................57