Intel IXP1200 manual Vctablehashed Structure

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

The OC-12 configuration uses a VC Table Cache in conjunction with the VC table, however the description of the backing VC table in this section applies with or without the presence of a VC Cache.

The VC table entry answers the following questions for the ATM Receive thread:

•Is the VC open? (If no, discard the cell)

•Which LLC/SNAP patterns are expected at the start of each PDU? (If no match, discard cell.)

•Which AAL is the VC open for? (ATM Receive currently processes only AAL5.)

•Where should ATM Receive put the payload in DRAM (buffer and offset)?

•For hardware CRC: what is the current syndrome for this PDU?

4.1.2VC_TABLE_HASHED Structure

VC_TABLE_HASHED supports the entire ATM VC name-space by employing the IXP12xx hashing hardware as follows:

•At initialization, microcode loads the hash48 multiplier CSRs with the largest prime number that fits into 48 bits: 0xffffffffffc5.

•At run-time, ATM Receive locates entries like so:

key = (atm_header & 0xFFFFFFF0) port#) hash_output = hash1_48[key]

Index = ((hash_output) ^ (hash_output >> 16) ^ (hash_output >> 32)) & 0xFFFF

The index is used to read an entry from a 64K entry "primary" hashed VC Table in SRAM. If the key in the entry matches the starting key, the hash table has successfully delivered the right VC table entry with just one SRAM read. If the key does not match the key in the entry read from the primary table, it follows a linked "collision" list threaded with the entry "Next" field (see figure Figure 23)

30 Application Note

Modified on: 3/20/02,