IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

For the synchronous empty->non-empty queue notification feature to be used, only one microengine can be assigned to dequeue from each queue. Further, it is optimal when threads on that microengine dequeue from a single queue rather than from multiple queues.

If the dequeuing thread services multiple queues, it can use packetq_send queues and associated dequeue code, or the polled scratchpad bit-vector notification mechanism can be added to these macros. Queue headers must be in SRAM, as these macros do not currently support scratchpad RAM headers

Figure 34. Buffer Descriptor Queue API

bdq_init()

Initialize queue structure.

 

 

bdq_enqueue()

Enqueue on Back.

 

 

bdq_dequeue()

Dequeue from Front.

 

 

Figure 35. Buffer Descriptor Queue Descriptor Structure (Resides in SRAM)

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Figure 36. Buffer Descriptor Queue Structure (Only Relevant Part Shown)

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4.8Counters

This design uses a counter subsystem wrapper around incrementing scratchpad RAM locations. The subsystem manages counter names, enabling and disabling counters at compile time, and pretty printing. Part of the counter subsystem runs on the microengines, and part on the StrongARM core

counters.uc provides the following microcode API:

•counter_reset()

•counter_inc()

•port_counter_inc()

counters.c provides the following API to the Transactor command prompt as well as VxWorks console (neither macro requires parameters):

•counters_init()

•counters_print()

The counter names are allocated in system_config.h.

•In simulation, counters.c is compiled into the atm_utils.dll Transactor foreign model.

46

Application Note

Modified on: 3/20/02,

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Intel IXP1200 manual Counters
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