Intel IXP1200 port_counter_inc() Algorithm, Example

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

50 Application Note

Modified on: 3/20/02,

port_counter_inc() Algorithm

#if (IN_ENABLE_FLAGS & COUNTERS_ENABLE_MASK)

addr = IN_PORT_COUNTERS_BASE + 16 * (IN_PORT_BASE + in_port_index) +

IN_EXCEPTION_INDEX

*addr += 1

#endif

#if (IN_ENABLE_FLAGS & COUNT_PORT_EXCEPTIONS)

IN_TOTAL_DISCARDS += 1

#endif

Example

#define COUNT_PORT_EVENTS (1 << 11) // normal port activity

#define COUNT_PORT_EXCEPTIONS (1 << 12) // per-port exceptions

The 16 per-port counters are named by various include files, as summarized by the string table that

counters_print() uses to prin t the per-port counters:

char *port_counter_strings [] = {

"PORT_FULLQ",//0x00 port.uc

"PORT_RXERROR", //0x01 port.uc

"PORT_RXFAIL",//0x02 port.uc

"port counter 3",

"PORT_RXCANCEL",//0x04 port.uc

"PORT_SHDBE_SOP",//0x05 port.uc

"PORT_SHDBE_NOT_SOP", //0x06 port.uc

"port counter 7",

"IP_BAD_TOTAL_LENGTH", //0x08 ip.uc

"IP_BAD_TTL", //0x09 ip.uc

"IP_BAD_CHECKSUM", //0x0a ip.uc

"IP_NO_ROUTE", //0x0b ip.uc

"IP_INVALID_ADDRESS", //0x0c ip.uc

"MAC_INVALID_ADDRESS", //0x0d ether.uc

"IP_DBCAST_ADDRESS", //0x0e ip.uc

"PORT_DISABLED", //0x0f ip.uc

#define PORT_EXCEPTION EXCEPTION_COUNTERS, TOTAL_DISCARDS, ATM_PORT3,

COUNT_PORT_EXCEPTIONS

port_counter_inc(port_idx, ATM_PORT0, PORT_FULLQ, PORT_EXCEPTION)

IN_TOTAL_DISCARDS Address of global discard counter.

IN_MAX_PORT_NUMBER

Highest valid port number -- from a per-port counters point of view.

If the sum of IN_PORT_BASE and in_port_index exceeds

IN_MAX_PORT_NUMBER, then the port number is truncated to

IN_MAX_PORT_NUMBER. This allows limiting the scratchpad

RAM dedicated to counters while still allowing event counting on

very high numbered ports (e.g., logical ports used by the

StrongARM core)

IN_ENABLE_FLAGS

Counter increment flag. Must match the

COUNTERS_ENABLE_MASK bit. If set to

COUNT_PORT_EXCEPTIONS, the global counter at

IN_TOTAL_DISCARDS will be incremented in addition to the per-

port counter.

Parameter Description

Contents

Main Application Note Contents Page Page Figures 1.0 Introduction 1.1 Purpose of ATM Example Design 1.2 Scope of Example Design 1.2.1 Supported / Not Implemented Functions 1.3 Background 1.3.1 Ethernet, IP and AAL5 Protocol Processing 1.3.2 Frame and PDU Length vs. IP Packet Length 1.3.3 Expected Ethernet Transmit Bandwidth 1.4 Execution Environment 1.4.1 Software Page 1.4.2 Hardware 2.0 System Overview 2.1 System Programming Model 2.2 StrongARM Core Software 2.3 Software Partitioning Modified on: 3/20/02, 2.3.1 Lookup Tables Not shown in the diagrams, the microengines make use of either three or four lookup tables: Route microengine and the Ethernet Receive microengine. verification. * Modified on: 3/20/02, 2.4.1.2 IP Lookup Table Modified on: 3/20/02, 2.4.2 Ethernet to ATM D at a Flo w 2.5 StrongARM Core Initialization 2.6 Microengine Initialization 3.0 Microengine Functional Blocks 3.1 ATM Receive Microengine 3.1.1 Structure Application Note 21 Modified on: 3/20/02, 3.1.2 High Level Algorithm Figure 12. ATM Receive High Level Algorithm if(ATM header hits in VC cach 3.2 ATM Transmit Microengine 3.2.1 High Level Algorithm 3.3 IP-Router Microengine 3.3.1 Structure 3.3.2 High Level Algorithm 3.4 Ethernet Receive Microengine 3.5 Ethernet Transmit Microengine 3.5.1 Ethernet Transmit Structure 3.5.2 High Level Algorithm 3.6 CRC-32 Calculations using IXP1240/1250 Hardware 3.6.1 CRC-32 Hardware Checking on Receive Page 3.6.2 CRC-32 Hardware Generation on Transmit 3.6.2.1 Transmit Alignment 3.7 CRC-32 Checker and Generator Microengines (Soft-CRC) 3.7.2 CRC -32 Checker and Generator High Level Algorithm 3.7.3 CRC-32 Computation 4.0 Software Subsystems & Data Structures 4.1 Virtual Circuit Lookup Table - atm_vc_table.uc 4.1.1 VC Table Function Page 4.1.3 VC_TABLE_LINEAR Structure . . . 4.1.4 VC Table Management API - atm_utils.c 4.1.5 VC Table Entry Modified on: 3/20/02, Figure 24. VC Lookup Table Entry (VC_TABLE_LINEAR) 4.2 Virtual Circuit Lookup Table Cache 4.2.1 VC Cache Function 4.2.1.1 OC-12 Configuration 4.2.1.2 OC-3 Configuration 4.2.2 VC Cache Structure 4.2.3 VC Cache API 4.3 IP Lookup Table 4.3.1 IP Table Function 4.3.2 IP Table Structure 4.3.3 IP Table Management API 4.3.3.1 route_table_init() 4.3.3.2 mtu_change() 4.3.3.3 atm_route_add() 4.3.3.4 enet_route_add() 4.3.3.5 rt_ent_info() 4.3.3.6 route_delete() 4.3.3.7 rt_help () 4.3.4 IP Route Table Entry 4.4 SRAM Buffer Descriptors and DRAM Data Buffers Figure 25. IP Route Table Entry - ATM Destination Figure 26. IP Route Table Entry - Ethernet Destination Modified on: 3/20/02, SRAM 4.4.1 SRAM Buffer Descriptor Format Figure 27. SRAM Descriptor to DRAM Buffer Mapping SRAM Figure 28. Buffer Descriptor Format for ATM Transmit Destination Port Modified on: 3/20/02, 4.4.2 DRAM Data Buffer Format Figure 29. Buffer Descriptor Format for Ethernet Transmit Destination Port Figure 30. DRAM Data Buffer Format - 12 Byte Offset (Received by ATM) Figure 31. DRAM Data Buffer Format - 6 Byte Offset (Received by ATM, Transmitted by Ethernet) Figure 32. DRAM Data Buffer Format - 6 Byte Offset (Received by Ethernet, Transmitted by ATM) 4.5 Sequence Numbers - sequence.uc 4.5.1 SEQUENCE_HANDLE Usage 4.5.2 Usage Model 4.5.2.1 Example 4.6 Message Queues - msgq.uc 4.6.1 MSGQ_HANDLE Parameters 4.6.2 msgq_init_queue() 4.6.3 msgq_init_regs() 4.6.4 msgq_send() Modified on: 3/20/02, 4.6.5 msgq_receive() Receives a message from the queue. 4.6.6 Example 4.7 Buffer Descriptor Queues - bdq.uc 4.7.1 BDQ Manag ement Macros 4.7.1.1 Features 4.7.1.2 Limitations 4.8 Counters Page 4.8.2.3 Global Counter Enable and Flags Global Counter Enable and Flags Counter Flags Modified on: 3/20/02, 4.8.3 counters.uc 4.8.3.1 counter_reset() Resets the specified counter to zero. 4.8.3.2 counter_inc() Increments the specified counter. 4.8.3.3 port_counter_inc() port_counter_inc() Algorithm Example Modified on: 3/20/02, 4.8.4 counters.c 4.8.4.1 counters_init() Initializes all counters. 4.8.4.2 counters_print() Prints the names and values of all counters. Example 4.9 Global $transfer Register Name Manager - xfer.uc 4.10 Mutex Vectors 4.10.1 mutex_vector_init() 4.10.2 mutex_vector_enter() 4.10.3 mutex_vector_exit() 4.11 Inter-Thread Signalling 5.0 Project Configuration / Modifying the Example Design 5.1 project_config.h 5.2 system_config.h 5.3 Switching Between Hardware Configurations 6.0 Testing Environments 7.0 Simulation Support (Scripts, etc.) 8.0 Limitations 9.0 Extending the Example Design Modified on: 3/20/02, 10.0 Document Conventions 11.0 Acronyms & Definitions Figure 37. Illustration of Array of 32-bit Words Figure 38. Illustration of Byte Sequence Figure 39. Definitions 12.0 Related Documents Modified on: 3/20/02, Figure 39. Definitions (Continued)