IXP1200 Network Processor Family

IXP1200 Network Processor Family

ATM OC-3/12/Ethernet IP Router Example Design

Application Note - Rev 1.0, 3/20/2002

Order Number: 278393-001

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Intel manual IXP1200 Network Processor Family

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol Processing SAR Frame and PDU Length vs. IP Packet Length Frame and PDU Length vs. IP Packet Length Expected Ethernet Transmit Bandwidth Software Execution Environment Developer’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware System Programming Model StrongARM Core Software ATM TX Software Partitioning Lookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup Table Ethernet to ATM Data Flow StrongARM Core Initialization Microengine Initialization Microengine Functional BlocksATM Receive Microengine Structure OC-12 Port OC-3 Ports High Level Algorithm ATM Transmit High Level Algorithm ATM Transmit Microengine Ethernet Receive Microengine IP-Router Microengine Ethernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian Diagram Transmit Alignment CRC-32 Hardware Generation on Transmit Functional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRC Virtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 Computation Vctablehashed Structure Primary VC Table Vctablelinear Structure VC Table Entry VC Table Management API atmutils.c Buffer Offset Buffer Index Entry DescriptionCell data11 Entry Description 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache Structure VC Cache API IP Lookup TableIP Table Function IP Table Structure Routetableinit IP Table Management APIMtuchange Atmrouteadd Rtentinfo EnetrouteaddRoutedelete Rthelp 2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data Buffers Next BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdr System Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call Description Usage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line Analogy Msgqinitqueue Msgqhandle ParametersMsgqinitregs Msgqsend Ramoption Msgqreceive Feature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management Macros Count Counters Use of the Counter Subsystem Global ParametersCounter Base Address Counter Index Counter Flags Global Counter Enable and Flags#define Statement Description Counter Group Description Counterinc Counters.uc CounterresetPortcounterinc Intotaldiscards Portcounterinc Algorithm Countersprint Counters.c Countersinit Atmtxcrcbadbd Global $transfer Register Name Manager xfer.uc Mutexvectorinit Mutex VectorsMutexvectorenter Mutexvectorexit Inter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... Bytes Title Description Related Documents