IP Lookup Table, ATM to Ethernet Processing Steps | Intel IXP1200

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

syndrome is updated appropriately. The VC Table Entry also contains an AAL type field. Currently, this example design supports only classical IP over ATM, where the AAL type can be either 0 or 5. A value of 0 indicates that the VC is not open, so any cell received on that VC is immediately discarded.

The LLC/SNAP field specifies the protocol type. Currently, the only valid value is 0x AA AA 03 00 00 00 08 00 (classical IP over ATM). While this implementation consumes and produces just one valid LLC/SNAP pattern, this pattern is not hard-coded. The LLC/SNAP bits are included in the IP route table entry, as well as the VC lookup table. This is to make it easy to modify the design, not only support a different LLC/SNAP pattern, but also to be able to support different valid patterns for each VC.

2.4.1.2IP Lookup Table

Each PDU contains an IP header in its first cell. Therefore, a single IP lookup is performed for each PDU, regardless of the number of cells in the PDU.

Figure 10. ATM to Ethernet Processing Steps

SDRAM

Check CRC

Packet Buffer

ATM PDU on Rx Port

on AAL-5 PDU

Cell N

7

(40 Bytes)

Ethernet PDU on Tx Port

1

Receive

Cell 1

ATM Cell

If end of PDU

Transmit 10

(48 Bytes)

ATM

LLC

IP

Payload

ATM

PAD

CLP

UU

LEN

CRC

MPKT

Hdr

Hdr

Hdr

Hdr

5

Cell 0

(48 Bytes)

		Move		Ether
6		payload		Hdr
Check		to buffer		IP Payload
length				IP Payload
length
8		7
Strip	Check
AAL-5	CRC
trailer				Build MPKT,
	IP look-up		9	Build MPKT,
3	IP look-up			add Ethernet
IP	on first cell			header on first
IP	Route Table			MPKT
Lookup				MPKT
Lookup
IP	Port	Port	Enet
Address	type	number	header
VC Lookup Table Entry			4 Locate buffer & offset
VC Lookup Table Entry

		VPI/VCI	AAL	LLC/SNAP	Buffer	Buffer base	CRC-32
VC Look-up check	2		type	header	offset	address	Residue
LLC/SNAP header	2

on first cell

A9638-01

18	Application Note

Modified on: 3/20/02,

Image 18

Intel IXP1200 manual IP Lookup Table, ATM to Ethernet Processing Steps

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol Processing Frame and PDU Length vs. IP Packet Length SAR Expected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet Length Execution Environment Software Developer’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming Model Software Partitioning ATM TX Lookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing Steps StrongARM Core Initialization Ethernet to ATM Data Flow ATM Receive Microengine Microengine Functional BlocksMicroengine Initialization Structure High Level Algorithm OC-12 Port OC-3 Ports ATM Transmit Microengine ATM Transmit High Level Algorithm IP-Router Microengine Ethernet Receive Microengine Ethernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in Dram CRC-32 Hardware Generation on Transmit Transmit Alignment CRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and Generator CRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Computation Vctablehashed Structure Vctablelinear Structure Primary VC Table VC Table Management API atmutils.c VC Table Entry Entry Description Buffer Offset Buffer IndexCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache Structure IP Table Function IP Lookup TableVC Cache API IP Table Structure Mtuchange IP Table Management APIRoutetableinit Atmrouteadd Routedelete EnetrouteaddRtentinfo Rthelp Sram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8 Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdr Sequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call Description Example Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line Analogy Msgqinitregs Msgqhandle ParametersMsgqinitqueue Msgqsend Msgqreceive Ramoption Buffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management Macros Counters Count Counter Base Address Global ParametersUse of the Counter Subsystem Counter Index #define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group Description Counters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm Intotaldiscards Counters.c Countersinit Countersprint Global $transfer Register Name Manager xfer.uc Atmtxcrcbadbd Mutexvectorenter Mutex VectorsMutexvectorinit Mutexvectorexit Project Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... Bytes Related Documents Title Description