IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design
Application Note 39

Modified on: 3/20/02,

Both descriptors and buffers are stored in arrays. The array index is used to associate a unique

DRAM Data Buffer with each SRAM Descriptor:

4.4.1 SRAM Buffer Descriptor Format

This buffer descriptor format is used throughout the design, except when a descriptor is enqueued

onto a packet_queue for Ethernet transmit.

Figure 27. SRAM Descriptor to DRAM Buffer Mapping

A9783-01

SRAM

SRAM

descriptor [i+1]
descriptor [i]
descriptor [i+2]
data buffer [i+1]
data buffer [i]
data buffer [i+2]

Figure 28. Buffer Descriptor Format for ATM Transmit Destination Port

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09876543210
0Z Next BD
1 Last Quad X
2 Queue Index Start Byte Offset Y
3 ATM Header
Entry Description
Z Unused - will be overwritten upon enqueue/dequeue address updates
Next BD 32-bit SRAM address of the next buffer descriptor in the same queue
Last Quad Offset of the last quadword in the buffer that contains data
X Unused - will be erased every time LAST_QUAD is updated, Rx any cell
Queue Index Index of the queue where this descriptor came from
Start Byte Offset Offset of the first byte of data to be transmitted
Y Unused - will be erased every tim e Start byte offset is updated, Rx first cell -- Tx any cell
ATM Header ATM Header (w/o HEC) to be attached to each cell of the PDU in the buffer