Lookup Tables | Intel IXP1200 instruction

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

In the OC-12 configuration, there are two message queues (MSGQs) in scratchpad RAM, one for PDUs from each Ethernet Receive microengine. The pool of threads in the ATM transmit microengine alternately poll the two MSGQs.

In the OC-3 configurations, there is a buffer descriptor queue (BDQ) in SRAM associated with each ATM transmit port. BDQs are similar to packetqs, but they are slightly more efficient in configurations, where for example the transmitter dedicates a thread to each BDQ.

Figure 8. IXP1240 OC-3 4xATM and 8xEthernet 100Mbps Microengine Partitioning

	ATM RX
OC-3	Port 8
OC-3	Port 9
OC-3	MSGQ
OC-3	Port 10
OC-3	Port 11

IPR

IP Route

IP Route

IP Route

IP Route

PktQ

PktQ

PktQ

PktQ

PktQ

PktQ

PktQ

PktQ

Ethernet TX

Scheduler

Fill

Fill

Fill

Ethernet

Ethernet

Ethernet

Ethernet

Ethernet

Ethernet

Ethernet

Ethernet

ATM TX

OC-3	Port 8	BDQ
OC-3	Port 9	BDQ
OC-3	Port 10	BDQ
OC-3	Port 11	BDQ

Legend:

Ethernet RX

Port4

Port5

Port6

Port7

Ethernet RX
	Port0	Ethernet
	Port1	Ethernet
	Port2	Ethernet
Ethernet	Port3	Ethernet
Ethernet
Ethernet
Ethernet

= Thread		=	Scratchpad
= Microengine			Memory	= MSGQ
= Physical Port		=	SRAM

2.3.1Lookup Tables

Not shown in the diagrams, the microengines make use of either three or four lookup tables:

•VC Lookup Table - resides in SRAM and is used by the ATM Receive microengine.

•IP Lookup Table - resides partially in SRAM and partially in DRAM, and is used by the IP Route microengine and the Ethernet Receive microengine.

•MAC Address Hash Table - resides in SRAM and is used for RFC 1812 Port address verification.

•Software CRC configurations use a table of pre-computed CRC-32 syndromes in SRAM.

16	Application Note

Modified on: 3/20/02,

Image 16

Intel IXP1200 manual Lookup Tables

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol Processing Frame and PDU Length vs. IP Packet Length SAR Expected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet Length Execution Environment Software Developer’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware StrongARM Core Software System Programming Model Software Partitioning ATM TX Lookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing Steps StrongARM Core Initialization Ethernet to ATM Data Flow Microengine Functional Blocks Microengine InitializationATM Receive Microengine Structure High Level Algorithm OC-12 Port OC-3 Ports ATM Transmit Microengine ATM Transmit High Level Algorithm IP-Router Microengine Ethernet Receive Microengine Ethernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in Dram CRC-32 Hardware Generation on Transmit Transmit Alignment CRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and Generator Software Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 Computation Vctablehashed Structure Vctablelinear Structure Primary VC Table VC Table Management API atmutils.c VC Table Entry Buffer Offset Buffer Index Entry DescriptionCell data11 Entry Description VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache Structure IP Lookup Table VC Cache APIIP Table Function IP Table Structure IP Table Management API RoutetableinitMtuchange Atmrouteadd Enetrouteadd RtentinfoRoutedelete Rthelp Sram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8 Next BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdr Sequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call Description Message Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line Analogy Msgqhandle Parameters MsgqinitqueueMsgqinitregs Msgqsend Msgqreceive Ramoption 1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management Macros Counters Count Global Parameters Use of the Counter SubsystemCounter Base Address Counter Index Global Counter Enable and Flags Counter Flags#define Statement Description Counter Group Description Counterinc Counters.uc CounterresetPortcounterinc Portcounterinc Algorithm Intotaldiscards Counters.c Countersinit Countersprint Global $transfer Register Name Manager xfer.uc Atmtxcrcbadbd Mutex Vectors MutexvectorinitMutexvectorenter Mutexvectorexit Inter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... Bytes Related Documents Title Description