IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design
16 Application Note

Modified on: 3/20/02,

In the OC-12 configuration, there are two message queues (MSGQs) in scratchpad RAM, one for

PDUs from each Ethernet Receive microengine. The pool of threads in the ATM transmit

microengine alternately poll the two MSGQs.

In the OC-3 configurations, there is a buffer descriptor queue (BDQ) in SRAM associated with

each ATM transmit port. BDQs are similar to packetqs, but they are slightly more efficient in

configurations, where for example the transmitter dedicates a thread to each BDQ.

Figure 8. IXP1240 OC-3 4xATM and 8xEthernet 100Mbps Microengine Partitioning

2.3.1 Lookup Tables

Not shown in the diagrams, the microengines make use of either three or four lookup tables:

VC Lookup Table - resides in SRAM and is used by the ATM Receive microengine.
IP Lookup Table - resides partially in SRAM and partially in DRAM, and is used by the IP

Route microengine and the Ethernet Receive microengine.

MAC Address Hash Table - resides in SRAM and is used for RFC 1812 Port address

verification.

Software CRC configurations use a table of pre-computed CRC-32 syndromes in SRAM.
Legend:
= Thread
= Microengine
= Physical Port
= Scratchpad
Memory
= SRAM = MSGQ
Port4
Ethernet RX
Port5
Port6
Port7
Ethernet
Ethernet
Ethernet
Ethernet
PktQ
PktQ
PktQ
PktQ
PktQ
PktQ
PktQ
PktQ
Scheduler
Ethernet TX
Fill
Fill
Fill
Port0
Ethernet RX
Port1
Port2
Port3
Port 8
ATM TX
Port 9
Port 10
Port 11
IP Route
IPR
IP Route
IP Route
IP Route
Port 8
ATM RX
Port 9
Port 10
Port 11
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
OC-3
OC-3
OC-3
OC-3
OC-3
OC-3
OC-3
OC-3
BDQ
BDQ
BDQ
BDQ
Ethernet
Ethernet
Ethernet
Ethernet
MSGQ