INSTALLATION PROCEDURE
Figure 4-7 PLO Pin Assignment for Receiving Clock (4-IMG System)
PLO input leads appear on the LT connectors labeled EXCLK0 and EXCLK1.
PLO mounting slots
PLO card is mounted in slots 21 and 23 of TSWM.
TSWM
LT cable connectors
Connect LT cables to the connectors labeled 
EXCLK0 
and 
EXCLK1
on the TSWM backplane.
Front View
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EXCLK0 |
| EXCLK1 |
PLO |
| PLO |
TSW
Backplane
EXCLK1 |
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TSWM
EXCLK0/EXCLK1 connector Pin Assignment
Pins are assigned as follows on 
EXCLK0/EXCLK1
connector. When clock is distributed from a digital interface,
use one pair of 
DIUxxx
leads among a maximum of 4 inputs. DIU leads have the following precedence: DIU0xx(High) 
DIU3xx(Low). On the contrary, to receive clock from an external 
DCSxx
leads.
34PH EXCLK
EXCLK1 
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| 30 | SYN1B | 5 | SYN1A |
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| 34PH EXCLK | Installation Cable |
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CHAPTER 4 |
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Page 38
Issue 2
