SSRAM
•
•Organized as 512K x 36 bits
•Accessible as memory for the Nios II processor and by the
SDRAM
•Two
•Organized as 4M x 16 bits x 4 banks
•Accessible as memory for the Nios II processor and by the
Flash memory
•
•Support both byte and word mode access
•Accessible as memory for the Nios II processor and by the
SD card socket
•Provides SPI and
•Accessible as memory for the Nios II processor with the
Pushbutton switches
•4 pushbutton switches
•Debounced by a Schmitt trigger circuit
•Normally high; generates one
Toggle switches
•18 toggle switches for user inputs
•A switch causes logic 0 when in the DOWN (closest to the edge of the
Clock inputs
•
•
•SMA external clock input
7