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Sigma protection registors and diodes not shown for other ports, DE2-70 User Manual, 1.8V 2.5V

Models: DE2-70

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1.8V 2.5V 3.3V

DE2-70 User Manual

1.8V 2.5V 3.3V

2 4 6

JP1

1 3 5

Figure 5.10. JP1 pin settings.

VCCIO5

VCCIO5

D12		D14
1		1	GPIO_D1
3	GPIO_D0	3	GPIO_D1
2		2
BAT54S		BAT54S

GPIO_D0	R51	47	IO_A0
GPIO_D1	R52	47	IO_A1

(protection registors and diodes not shown for other ports)

				(GPIO 0)
				J4
		IO_CLKINn0	1	2
		IO_CLKINp0	3	4
		IO_A2	5	6
		IO_A4	7	8
		IO_A6	9	10
	VCC5	IO_A8	11	12
	VCC5		13	14
			13	14
		IO_A10	15	16
		IO_A12	17	18
		IO_CLKOUTn0	19	20
		IO_CLKOUTp0	21	22
		IO_A16	21	22
		IO_A16	23	24
		IO_A18	25	26
		IO_A20	27	28
	VCC33	IO_A22	29	30
	VCC33		31	32
			31	32
		IO_A24	33	34
		IO_A26	35	36
		IO_A28	37	38
		IO_A30	39	40

IO_A0

IO_A1

IO_A3

IO_A5 IO_A7

IO_A9 IO_A11 IO_A13 IO_A14

IO_A15

IO_A17 IO_A19

IO_A21

IO_A23 IO_A25 IO_A27

IO_A29

IO_A31

VCCIO5

VCCIO5

D48		D50
1	GPIO_D32	1
3	GPIO_D32	GPIO_D33
3		3
2		2
BAT54S		BAT54S

GPIO_D32	R60	47	IO_B0
GPIO_D33	R61	47	IO_B1

(protection registors and diodes not shown for other ports)

			BOX Header 2X20M
				(GPIO 1)
				J5
		IO_CLKINn1	1	2
		IO_CLKINp1	3	4
		IO_B2	5	6
		IO_B4	7	8
		IO_B6	9	10
	VCC5	IO_B8	11	12
	VCC5		13	14
			13	14
		IO_B10	15	16
		IO_B12	17	18
		IO_CLKOUTn1		20
			19	20
		IO_CLKOUTp1		22
		IO_B16	21	22
		IO_B16	23	24
		IO_B18	25	26
		IO_B20	27	28
	VCC33	IO_B22	29	30
	VCC33		31	32
			31	32
		IO_B24	33	34
		IO_B26	35	36
		IO_B28	37	38
		IO_B30	39	40

IO_B0 IO_B1 IO_B3

IO_B5 IO_B7

IO_B9 IO_B11 IO_B13 IO_B14

IO_B15 IO_B17 IO_B19 IO_B21

IO_B23 IO_B25 IO_B27 IO_B29 IO_B31

BOX Header 2X20M

Figure 5.11. Schematic diagram of the expansion headers.

Signal Name	FPGA Pin No.	Description

IO_A [0]	PIN_C30	GPIO Connection 0 IO[0]

IO_A [1]	PIN_C29	GPIO Connection 0 IO[1]

IO_A [2]	PIN_E28	GPIO Connection 0 IO[2]

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Sigma manual protection registors and diodes not shown for other ports, DE2-70 User Manual, 1.8V 2.5V, Gpio

Contents

Version Copyright 2007 Terasic TechnologiesAltera DE2 Board Chapter 5 Using the DE2-70 BoardChapter 3 DE2-70 Control Panel Chapter 4 DE2-70 Video UtilityChapter 6 Examples of Advanced Demonstrations Chapter 7 AppendixAltera DE2 Board DE2-70 Package 1.1 Package ContentsChapter DE2-70 User Manual1.2 The DE2-70 Board Assembly Terasic Technologies No. 356, Sec. 1, Fusing E. Rd 1.3 Getting HelpAltera Corporation 101 Innovation Drive San Jose, California, 95134 USA Email university@altera.comAltera DE2-70 Board 2.1 Layout and ComponentsChapter 2.2 Block Diagram of the DE2-70 Board Cyclone II 2C70 FPGA Serial Configuration device and USB Blaster circuitToggle switches Pushbutton switchesSSRAM SDRAMVGA output Audio CODECNTSC/PAL/ SECAM TV decoder circuit 10/100 Ethernet controllerSerial ports 2.3 Power-up the DE2-70 BoardIrDA transceiver Two 40-pin expansion headersThe LCD display shows Welcome to the Altera DE2-70 3.1 Control Panel Setup DE2-70 Control PanelChapter Figure 3.1. The DE2-70 Control Panel 3.2 Controlling the LEDs, 7-Segment Displays and LCD Display Figure 3.3. Controlling LEDs Figure 3.4. Controlling 7-SEG displayDE2-70 User Manual 3.3 Switches and Buttons 3.4 SDRAM/SSRAM/Flash Controller and Programmer Figure 3.7. Accessing the SDRAM-U1 3.5 USB Monitoring 3. Press Load Memory Content to a File button3.6 PS2 Device 3.7 SD CARD 3.8 Audio Playing and Recording Figure 3.11. Playing audio from a selected wave file 3.9 Overall Structure of the DE2-70 Control Panel Figure 3.13. The block diagram of the DE2-70 control panel DE2-70 User ManualFPGA/ SOPC 4.1 Video Utility Setup DE2-70 Video UtilityChapter 4.2 VGA Display 4.3 Video Capture 4.4 Overall Structure of the DE2-70 Video Utility Figure 4.4. Video Capture Block Diagram Using the DE2-70 Board 5.1 Configuring the Cyclone II FPGAChapter Configuring the FPGA in JTAG Mode Configuring the EPCS16 in AS ModeFPGA 5.2 Using the LEDs and Switches Figure 5.4. Schematic diagram of the pushbutton and toggle switches Signal Name Figure 5.5. Schematic diagram of the LEDsDE2-70 User Manual FPGA Pin NoTable 5.1. Pin assignments for the toggle switches Table 5.2. Pin assignments for the pushbutton switchesDE2-70 User Manual 5.3 Using the 7-segment Displays DE2-70 User Manual 5.4 Clock Circuitry Connector Figure 5.8. Block diagram of the clock distributionTable 5.5. Pin assignments for the clock inputs DE2-70 User Manual16 DIGIT LCD 5.5 Using the LCD Module5.6 Using the Expansion Header protection registors and diodes not shown for other ports protection registors and diodes not shown for other portsDE2-70 User Manual 1.8V 2.5VDE2-70 User Manual DE2-70 User Manual Table 5.8. Pin assignments for the expansion headers5.7 Using VGA Figure 5.13. VGA horizontal timing specification DE2-70 User Manual Table 5.11. ADV7123 pin assignments5.8 Using the 24-bit Audio CODEC 5.10 PS/2 Serial Port 5.9 RS-232 Serial Port5.11 Fast Ethernet Network Controller DE2-70 User Manual Figure 5.17. Fast Ethernet schematic5.12 TV Decoder DE2-70 User Manual Figure 5.18. TV Decoder schematic5.13 Implementing a TV Encoder 5.14 Using USB Host and Device http//techtrain.microchip.com/webseminars/documents/IrDABW.pdf 5.15 Using IrDA5.16 Using SDRAM/SRAM/Flash DE2-70 User Manual Figure 5.22. SDRAM schematicSDRAM0 SDRAM1Figure 5.24. Flash schematic Figure 5.23. SSRAM schematicDE2-70 User Manual SSRAM 512Kx36DRAM0A0 DE2-70 User ManualDRAM0CKE DE2-70 User ManualDE2-70 User Manual Table 5.19. SDRAM pin assignmentsSRAM Controller Address Status DE2-70 User ManualSRAM Processor Address Status SRAM Burst Address AdvanceDE2-70 User Manual Table 5.20. SSRAM pin assignmentsDE2-70 User Manual Table 5.21. Flash pin assignmentsInstalling the Demonstrations 6.1 DE2-70 Factory ConfigurationDemonstration Setup, File Locations, and Instructions Bit stream used DE270Default.sof or DE270Default.pof6.2 TV Box Demonstration monitor Figure 6.1. Block diagram of the TV box demonstrationBit stream used DE270TV.sof or DE270TV.pof Demonstration Setup, File Locations, and Instructions6.3 TV Box Picture in Picture PIP Demonstration Demonstration Setup, File Locations, and Instructions Bit stream used DE270TVPIP.sof or DE270TVPIP.pofsignal PiPpositionLoad the bit stream into FPGA 6.4 USB Paintbrush Bit stream used DE270NIOSHOSTMOUSEVGA.sof Project directory DE270NIOSHOSTMOUSEVGANios II Workspace DE270NIOSHOSTMOUSEVGA\Software Demonstration Setup, File Locations, and Instructions6.5 USB Device Bit stream used DE270NIOSDEVICELED.sof Project directory DE270NIOSDEVICELED\HWNios II Workspace DE270NIOSDEVICELED\HW\Software Demonstration Setup, File Locations, and Instructions6.6 A Karaoke Machine Bit stream used DE2-70i2sound.sof or DE2-70i2sound.pof Demonstration Setup, File Locations, and InstructionsFigure 6.9. Block diagram of the Karaoke Machine demonstration 6.7 Ethernet Packet Sending/Receiving MP3/Any Audio Output Speaker MicrophoneClock/Data Frequency Generator Demonstration Setup, File Locations, and Instructions 6.8 SD Card Music Player Figure 6.13. Block diagram of the SD music player demonstration Bit stream used DE270SDCardAudioPlayer.sof Project directory DE270SDCardAudioPlayerNios II Workspace DE270SDCardAudioPlayer\Software Demonstration Setup, File Locations, and Instructions6.9 Music Synthesizer Demonstration Figure 6.17 illustrates the setup for this demonstration Demonstration Setup, File Locations, and InstructionsBit stream used DE270Synthesizer.sof or DE2-70Synthesizer.pof Line Out DE2-70 User ManualSpeaker VGALCD/CRTMonitor6.10 Audio Recording and Playing SOPC Software Project directory DE270AUDIO\software\projectaudioDemonstration Setup, File Locations, and Instructions Load the Software Execution File into FPGA. note *1 Revision History AppendixCopyright Statement Chapter