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Sigma DE2-70 manual Using the Expansion Header

Models: DE2-70

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DE2-70 User Manual

LCD_DATA[5]	PIN_C2	LCD Data[5]

LCD_DATA[6]	PIN_C3	LCD Data[6]

LCD_DATA[7]	PIN_B2	LCD Data[7]

LCD_RW	PIN_F3	LCD Read/Write Select, 0 = Write, 1 = Read

LCD_EN	PIN_E2	LCD Enable

LCD_RS	PIN_F2	LCD Command/Data Select, 0 = Command, 1 = Data

LCD_ON	PIN_F1	LCD Power ON/OFF

LCD_BLON	PIN_G3	LCD Back Light ON/OFF

Table 5.6. Pin assignments for the LCD module.

Note that the current LCD modules used on DE2/DE2-70 boards do not have backlight. Therefore the LCD_BLON signal should not be used in users’ design projects.

5.6 Using the Expansion Header

The DE2-70 Board provides two 40-pin expansion headers. Each header connects directly to 36 pins of the Cyclone II FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins. Among these 36 I/O pins, 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA.

The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, or 1.8V using JP1. Because the expansion I/Os are connected to the BANK 5 of the FPGA and the VCCIO voltage (VCCIO5) of this bank is controlled by the header JP1, users can use a jumper to select the input voltage of VCCIO5 to 3.3V, 2.5V, and 1.8V to control the voltage level of the I/O pins. Table 5.7 lists the jumper settings of the JP1. The pin-outs of the JP1 appear in the Figure 5.10.

Finally, Figure 5.11 shows the related schematics. Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages. The figure shows the protection circuitry for only two of the pins on each header, but this circuitry is included for all 72 data pins. Table 5.8 gives the pin assignments.

	JP1 Jumper Settings	Supplied Voltage to VCCIO5	IO Voltage of Expansion
	JP1 Jumper Settings	Supplied Voltage to VCCIO5	Headers (J4/J5)
			Headers (J4/J5)

	Short Pins 1 and 2	1.8V	1.8V

	Short Pins 3 and 4	2.5V	2.5V

	Short Pins 5 and 6	3.3V	3.3V

Table 5.7. Voltage level setting of the expansion headers using JP1.

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Sigma DE2-70 manual Using the Expansion Header

Contents

Copyright 2007 Terasic Technologies VersionChapter 5 Using the DE2-70 Board Altera DE2 BoardChapter 3 DE2-70 Control Panel Chapter 4 DE2-70 Video UtilityAltera DE2 Board Chapter 6 Examples of Advanced DemonstrationsChapter 7 Appendix 1.1 Package Contents DE2-70 PackageChapter DE2-70 User Manual1.2 The DE2-70 Board Assembly 1.3 Getting Help Terasic Technologies No. 356, Sec. 1, Fusing E. RdAltera Corporation 101 Innovation Drive San Jose, California, 95134 USA Email university@altera.comChapter Altera DE2-70 Board2.1 Layout and Components 2.2 Block Diagram of the DE2-70 Board Serial Configuration device and USB Blaster circuit Cyclone II 2C70 FPGAPushbutton switches Toggle switchesSSRAM SDRAMAudio CODEC VGA outputNTSC/PAL/ SECAM TV decoder circuit 10/100 Ethernet controller2.3 Power-up the DE2-70 Board Serial portsIrDA transceiver Two 40-pin expansion headersThe LCD display shows Welcome to the Altera DE2-70 Chapter 3.1 Control Panel SetupDE2-70 Control Panel Figure 3.1. The DE2-70 Control Panel 3.2 Controlling the LEDs, 7-Segment Displays and LCD Display DE2-70 User Manual Figure 3.3. Controlling LEDsFigure 3.4. Controlling 7-SEG display 3.3 Switches and Buttons 3.4 SDRAM/SSRAM/Flash Controller and Programmer Figure 3.7. Accessing the SDRAM-U1 3. Press Load Memory Content to a File button 3.5 USB Monitoring3.6 PS2 Device 3.7 SD CARD 3.8 Audio Playing and Recording Figure 3.11. Playing audio from a selected wave file 3.9 Overall Structure of the DE2-70 Control Panel FPGA/ SOPC Figure 3.13. The block diagram of the DE2-70 control panelDE2-70 User Manual Chapter 4.1 Video Utility SetupDE2-70 Video Utility 4.2 VGA Display 4.3 Video Capture 4.4 Overall Structure of the DE2-70 Video Utility Figure 4.4. Video Capture Block Diagram Chapter Using the DE2-70 Board5.1 Configuring the Cyclone II FPGA FPGA Configuring the FPGA in JTAG ModeConfiguring the EPCS16 in AS Mode 5.2 Using the LEDs and Switches Figure 5.4. Schematic diagram of the pushbutton and toggle switches Figure 5.5. Schematic diagram of the LEDs Signal NameDE2-70 User Manual FPGA Pin NoDE2-70 User Manual Table 5.1. Pin assignments for the toggle switchesTable 5.2. Pin assignments for the pushbutton switches 5.3 Using the 7-segment Displays DE2-70 User Manual 5.4 Clock Circuitry Figure 5.8. Block diagram of the clock distribution ConnectorTable 5.5. Pin assignments for the clock inputs DE2-70 User Manual5.5 Using the LCD Module 16 DIGIT LCD5.6 Using the Expansion Header protection registors and diodes not shown for other ports protection registors and diodes not shown for other portsDE2-70 User Manual 1.8V 2.5VDE2-70 User Manual Table 5.8. Pin assignments for the expansion headers DE2-70 User Manual5.7 Using VGA Figure 5.13. VGA horizontal timing specification Table 5.11. ADV7123 pin assignments DE2-70 User Manual5.8 Using the 24-bit Audio CODEC 5.9 RS-232 Serial Port 5.10 PS/2 Serial Port5.11 Fast Ethernet Network Controller Figure 5.17. Fast Ethernet schematic DE2-70 User Manual5.12 TV Decoder Figure 5.18. TV Decoder schematic DE2-70 User Manual5.13 Implementing a TV Encoder 5.14 Using USB Host and Device 5.15 Using IrDA http//techtrain.microchip.com/webseminars/documents/IrDABW.pdf5.16 Using SDRAM/SRAM/Flash Figure 5.22. SDRAM schematic DE2-70 User ManualSDRAM0 SDRAM1Figure 5.23. SSRAM schematic Figure 5.24. Flash schematicDE2-70 User Manual SSRAM 512Kx36DE2-70 User Manual DRAM0A0DE2-70 User Manual DRAM0CKETable 5.19. SDRAM pin assignments DE2-70 User ManualDE2-70 User Manual SRAM Controller Address StatusSRAM Processor Address Status SRAM Burst Address AdvanceTable 5.20. SSRAM pin assignments DE2-70 User ManualTable 5.21. Flash pin assignments DE2-70 User Manual6.1 DE2-70 Factory Configuration Installing the DemonstrationsDemonstration Setup, File Locations, and Instructions Bit stream used DE270Default.sof or DE270Default.pof6.2 TV Box Demonstration Figure 6.1. Block diagram of the TV box demonstration monitorBit stream used DE270TV.sof or DE270TV.pof Demonstration Setup, File Locations, and Instructions6.3 TV Box Picture in Picture PIP Demonstration Bit stream used DE270TVPIP.sof or DE270TVPIP.pof Demonstration Setup, File Locations, and Instructionssignal PiPpositionLoad the bit stream into FPGA 6.4 USB Paintbrush Project directory DE270NIOSHOSTMOUSEVGA Bit stream used DE270NIOSHOSTMOUSEVGA.sofNios II Workspace DE270NIOSHOSTMOUSEVGA\Software Demonstration Setup, File Locations, and Instructions6.5 USB Device Project directory DE270NIOSDEVICELED\HW Bit stream used DE270NIOSDEVICELED.sofNios II Workspace DE270NIOSDEVICELED\HW\Software Demonstration Setup, File Locations, and Instructions6.6 A Karaoke Machine Figure 6.9. Block diagram of the Karaoke Machine demonstration Bit stream used DE2-70i2sound.sof or DE2-70i2sound.pofDemonstration Setup, File Locations, and Instructions Clock/Data Frequency Generator 6.7 Ethernet Packet Sending/ReceivingMP3/Any Audio Output Speaker Microphone Demonstration Setup, File Locations, and Instructions 6.8 SD Card Music Player Figure 6.13. Block diagram of the SD music player demonstration Project directory DE270SDCardAudioPlayer Bit stream used DE270SDCardAudioPlayer.sofNios II Workspace DE270SDCardAudioPlayer\Software Demonstration Setup, File Locations, and Instructions6.9 Music Synthesizer Demonstration Demonstration Setup, File Locations, and Instructions Figure 6.17 illustrates the setup for this demonstrationBit stream used DE270Synthesizer.sof or DE2-70Synthesizer.pof DE2-70 User Manual Line OutSpeaker VGALCD/CRTMonitor6.10 Audio Recording and Playing Demonstration Setup, File Locations, and Instructions SOPCSoftware Project directory DE270AUDIO\software\projectaudio Load the Software Execution File into FPGA. note *1 Appendix Revision HistoryCopyright Statement Chapter