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Sigma manual 17. Fast Ethernet schematic, DE2-70 User Manual

Models: DE2-70

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Figure 5.17. Fast Ethernet schematic.

DE2-70 User Manual

N_VCC33

NGND

L1

BEAD

N_VCC33

R72 4.7K

25MHZ ENET_RESET_n SPEED ACT ENET_CS_n

								ENET_D[0..15]
		J6		15	16						N_VCC25	L2
	11	J6										L2
				MNT1	MNT0
		D3		MNT1	MNT0		2
		D3				TD+	1
						TD+	1
N_VCC33	12					TD-	4	N_VCC25
	12	D4 YELLOW				CTT	4
		D4 YELLOW				CTT	5
						CTR	5
						CTR	3
	10					RD+	3
						RD+	6
		D2		NT1SM	NT0SM	RD-	6
		D2	GREEN			RD-
	9	D1	GREEN			CHSG	8		R73	R74	R75	R76
							8
N_VCC33


		RJ45INTLED		14	13			CHSGND	49.9	49.9	49.9	49.9
				14	13

CHSGND		C18	C19
		0.1u	0.1u
		NGND	NGND
R77	120	SPEED
R78	120	ACT

C17	BC36	BC37	R70	U9	48 47 46 45 44 43 42 41 40 39 38 37
C17	BC36	BC37	R70	U9				N_VCC33
					BGGND RXGND SD GND X1 X2 VDD TEST RST#PW LED1 LED2 CS#			N_VCC33
10u	0.1u	0.1u	6.8K		BGGND RXGND SD GND X1 X2 VDD TEST RST#PW LED1 LED2 CS#
10u	0.1u	0.1u	6.8K
								R71
								4.7K
			1	BGRES		IOW#	36	ENET_IOW_n
BEAD			2	BGRES		IOW#	35	ENET_IOR_n
BEAD			2	RXVDD25		IOR#	35	ENET_IOR_n
RX+			3	RXVDD25		IOR#	34	ENET_INT
RX+			3	RX+		INT	34	ENET_INT
RX-			4	RX+		INT	33
RX-			4	RX-		GND	33	ENET_CMD
	NGND		5	RX-		GND	32
			5	RXGND		CMD	32
			6	RXGND		CMD	31	ENET_D8
TX+			6	TXGND	DM9000A-8/16bit	GP1/SD8	31	ENET_D8
			7	TXGND		GP1/SD8	30		N_VCC33
			7	TX+		VDD	30	ENET_D9
TX-			8	TX+		VDD	29
TX-			8	TX-		GP2/SD9	29
			9	TX-	DM9000AE	GP2/SD9	28	ENET_D10
			9	TXVDD25	DM9000AE	GP3/SD10	28	ENET_D10
			10	TXVDD25		GP3/SD10	27	ENET_D11
			10	SD7		GP4/SD11	27	ENET_D11
			11	SD7		GP4/SD11	26	ENET_D12
			11	SD6		GP5/SD12	26	ENET_D12
			12	SD6		GP5/SD12	25	ENET_D13
			12	SD5		GP6/SD13	25	ENET_D13
				SD5		GP6/SD13
					SD4 SD3 GND SD2 SD1 SD0 EEDIO EEDCK EEDCS AKE/SD15 VDD LED3/SD14 W
					13 14 15 16 17 18 19 20 21 22 23 24
								ENET_D14	N_VCC33
								ENET_D14
								ENET_D15
								ENET_D0
								ENET_D1
								ENET_D2
								ENET_D3
								ENET_D4
								ENET_D5
								ENET_D6
								ENET_D7

Figure 5.17. Fast Ethernet schematic.

Signal Name	FPGA Pin No.	Description

ENET_DATA[0]	PIN_A23	DM9000A DATA[0]

ENET_DATA[1]	PIN_C22	DM9000A DATA[1]

ENET_DATA[2]	PIN_B22	DM9000A DATA[2]

ENET_DATA[3]	PIN_A22	DM9000A DATA[3]

ENET_DATA[4]	PIN_B21	DM9000A DATA[4]

ENET_DATA[5]	PIN_A21	DM9000A DATA[5]

ENET_DATA[6]	PIN_B20	DM9000A DATA[6]

ENET_DATA[7]	PIN_A20	DM9000A DATA[7]

ENET_DATA[8]	PIN_B26	DM9000A DATA[8]

ENET_DATA[9]	PIN_A26	DM9000A DATA[9]

ENET_DATA[10]	PIN_B25	DM9000A DATA[10]

ENET_DATA[11]	PIN_A25	DM9000A DATA[11]

ENET_DATA[12]	PIN_C24	DM9000A DATA[12]

ENET_DATA[13]	PIN_B24	DM9000A DATA[13]

ENET_DATA[14]	PIN_A24	DM9000A DATA[14]

ENET_DATA[15]	PIN_B23	DM9000A DATA[15]

ENET_CLK	PIN_D27	DM9000A Clock 25 MHz

ENET_CMD	PIN_B27	DM9000A Command/Data Select, 0 = Command, 1 = Data

		51

Image 54

Sigma manual 17. Fast Ethernet schematic, DE2-70 User Manual

Contents

Copyright 2007 Terasic Technologies VersionChapter 3 DE2-70 Control Panel Chapter 5 Using the DE2-70 BoardAltera DE2 Board Chapter 4 DE2-70 Video UtilityChapter 6 Examples of Advanced Demonstrations Chapter 7 AppendixAltera DE2 Board Chapter 1.1 Package ContentsDE2-70 Package DE2-70 User Manual1.2 The DE2-70 Board Assembly Altera Corporation 101 Innovation Drive 1.3 Getting HelpTerasic Technologies No. 356, Sec. 1, Fusing E. Rd San Jose, California, 95134 USA Email university@altera.comAltera DE2-70 Board 2.1 Layout and ComponentsChapter 2.2 Block Diagram of the DE2-70 Board Serial Configuration device and USB Blaster circuit Cyclone II 2C70 FPGASSRAM Pushbutton switchesToggle switches SDRAMNTSC/PAL/ SECAM TV decoder circuit Audio CODECVGA output 10/100 Ethernet controllerIrDA transceiver 2.3 Power-up the DE2-70 BoardSerial ports Two 40-pin expansion headersThe LCD display shows Welcome to the Altera DE2-70 3.1 Control Panel Setup DE2-70 Control PanelChapter Figure 3.1. The DE2-70 Control Panel 3.2 Controlling the LEDs, 7-Segment Displays and LCD Display Figure 3.3. Controlling LEDs Figure 3.4. Controlling 7-SEG displayDE2-70 User Manual 3.3 Switches and Buttons 3.4 SDRAM/SSRAM/Flash Controller and Programmer Figure 3.7. Accessing the SDRAM-U1 3. Press Load Memory Content to a File button 3.5 USB Monitoring3.6 PS2 Device 3.7 SD CARD 3.8 Audio Playing and Recording Figure 3.11. Playing audio from a selected wave file 3.9 Overall Structure of the DE2-70 Control Panel Figure 3.13. The block diagram of the DE2-70 control panel DE2-70 User ManualFPGA/ SOPC 4.1 Video Utility Setup DE2-70 Video UtilityChapter 4.2 VGA Display 4.3 Video Capture 4.4 Overall Structure of the DE2-70 Video Utility Figure 4.4. Video Capture Block Diagram Using the DE2-70 Board 5.1 Configuring the Cyclone II FPGAChapter Configuring the FPGA in JTAG Mode Configuring the EPCS16 in AS ModeFPGA 5.2 Using the LEDs and Switches Figure 5.4. Schematic diagram of the pushbutton and toggle switches DE2-70 User Manual Figure 5.5. Schematic diagram of the LEDsSignal Name FPGA Pin NoTable 5.1. Pin assignments for the toggle switches Table 5.2. Pin assignments for the pushbutton switchesDE2-70 User Manual 5.3 Using the 7-segment Displays DE2-70 User Manual 5.4 Clock Circuitry Table 5.5. Pin assignments for the clock inputs Figure 5.8. Block diagram of the clock distributionConnector DE2-70 User Manual5.5 Using the LCD Module 16 DIGIT LCD5.6 Using the Expansion Header DE2-70 User Manual protection registors and diodes not shown for other portsprotection registors and diodes not shown for other ports 1.8V 2.5VDE2-70 User Manual Table 5.8. Pin assignments for the expansion headers DE2-70 User Manual5.7 Using VGA Figure 5.13. VGA horizontal timing specification Table 5.11. ADV7123 pin assignments DE2-70 User Manual5.8 Using the 24-bit Audio CODEC 5.9 RS-232 Serial Port 5.10 PS/2 Serial Port5.11 Fast Ethernet Network Controller Figure 5.17. Fast Ethernet schematic DE2-70 User Manual5.12 TV Decoder Figure 5.18. TV Decoder schematic DE2-70 User Manual5.13 Implementing a TV Encoder 5.14 Using USB Host and Device 5.15 Using IrDA http//techtrain.microchip.com/webseminars/documents/IrDABW.pdf5.16 Using SDRAM/SRAM/Flash SDRAM0 Figure 5.22. SDRAM schematicDE2-70 User Manual SDRAM1DE2-70 User Manual Figure 5.23. SSRAM schematicFigure 5.24. Flash schematic SSRAM 512Kx36DE2-70 User Manual DRAM0A0DE2-70 User Manual DRAM0CKETable 5.19. SDRAM pin assignments DE2-70 User ManualSRAM Processor Address Status DE2-70 User ManualSRAM Controller Address Status SRAM Burst Address AdvanceTable 5.20. SSRAM pin assignments DE2-70 User ManualTable 5.21. Flash pin assignments DE2-70 User ManualDemonstration Setup, File Locations, and Instructions 6.1 DE2-70 Factory ConfigurationInstalling the Demonstrations Bit stream used DE270Default.sof or DE270Default.pof6.2 TV Box Demonstration Bit stream used DE270TV.sof or DE270TV.pof Figure 6.1. Block diagram of the TV box demonstrationmonitor Demonstration Setup, File Locations, and Instructions6.3 TV Box Picture in Picture PIP Demonstration signal Bit stream used DE270TVPIP.sof or DE270TVPIP.pofDemonstration Setup, File Locations, and Instructions PiPpositionLoad the bit stream into FPGA 6.4 USB Paintbrush Nios II Workspace DE270NIOSHOSTMOUSEVGA\Software Project directory DE270NIOSHOSTMOUSEVGABit stream used DE270NIOSHOSTMOUSEVGA.sof Demonstration Setup, File Locations, and Instructions6.5 USB Device Nios II Workspace DE270NIOSDEVICELED\HW\Software Project directory DE270NIOSDEVICELED\HWBit stream used DE270NIOSDEVICELED.sof Demonstration Setup, File Locations, and Instructions6.6 A Karaoke Machine Bit stream used DE2-70i2sound.sof or DE2-70i2sound.pof Demonstration Setup, File Locations, and InstructionsFigure 6.9. Block diagram of the Karaoke Machine demonstration 6.7 Ethernet Packet Sending/Receiving MP3/Any Audio Output Speaker MicrophoneClock/Data Frequency Generator Demonstration Setup, File Locations, and Instructions 6.8 SD Card Music Player Figure 6.13. Block diagram of the SD music player demonstration Nios II Workspace DE270SDCardAudioPlayer\Software Project directory DE270SDCardAudioPlayerBit stream used DE270SDCardAudioPlayer.sof Demonstration Setup, File Locations, and Instructions6.9 Music Synthesizer Demonstration Demonstration Setup, File Locations, and Instructions Figure 6.17 illustrates the setup for this demonstrationBit stream used DE270Synthesizer.sof or DE2-70Synthesizer.pof VGALCD/CRTMonitor Line OutSpeaker VGA Out Keyboard Input6.10 Audio Recording and Playing SOPC Software Project directory DE270AUDIO\software\projectaudioDemonstration Setup, File Locations, and Instructions Load the Software Execution File into FPGA. note *1 Copyright Statement AppendixRevision History Chapter