hardware part is built by SOPC Builder under Quartus II. The hardware part includes all the other blocks. The “AUDIO Controller” is a
The audio chip is programmed through I2C protocol which is implemented in C code. The I2C pin from audio chip is connected to SOPC System Interconnect Fabric through PIO controllers. In this example, the audio chip is configured in Master Mode. The audio interface is configured as I2S and
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50M Hz |
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RESE_N |
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NIOS II |
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| SRAM | SRAM | Nios II |
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| UART | PIO | LED/KEY/SW/I2C |
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Clock | PLL | LCD | LCD |
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Controller |
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SDRAM |
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SRAM |
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| AUDIO | AUDIO |
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Figure 6.19. Block diagram of the audio recorder and player.
Demonstration Setup, File Locations, and Instructions
•Hardware Project directory: DE2_70_AUDIO
•Bit stream used: DE2P_TOP.sof
•Software Project directory: DE2_70_AUDIO\software\project_audio
•Software Execution File: DE2_70_AUDIO\software\project_auido\audio\debug\audio.elf
•Connect an Audio Source to the
•Connect a Microphone to
•Connect a speaker or headset to
•Load the bit stream into FPGA. (note *1)
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