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Sigma DE2-70 Bit stream used DE270TVPIP.sof or DE270TVPIP.pof, PiPposition, Sub window, signal

Models: DE2-70

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PiP_position_

DE2-70 User Manual

described in the section 6.2. The Composite_to_VGA block takes the video signals from the TV decoders as input and generate VGA-interfaced signals as output. The circuit in the FPGA is equipped with two Composite_to_VGA blocks converting the video signals from the TV decoder 1 and TV decoder 2 respectively. To display two video signals in PIP mode on the LCD/CRT monitor, the output VGA data rate of the Composite_to_VGA block for the sub window must be two times as fast as the rate of the Composite_to_VGA block for the main window. In addition, the output timing of the VGA interface signal from the Composite_to_VGA block is controlled by the pip_position_controller block that determines the stating poison of the sub window. Finally, both of the two VGA interfaced signals will be multiplexed and sent to the LCD/CRT monitor via the VGA_multiplexer block.

Video in 1

or

Video in 2

Video in 2

or

Video in 1

TV decoder

(Sub window)

TV decoder

(Main window)

	TD data	Composite_to_	VGA data
		Composite_to_	PiP_position_
	TD_clock	VGA	PiP_position_
		VGA	controller
		(Sub window)	controller
		(Sub window)
			Control
			signal
	TD_clock_	54Mhz		VGA data(Sub)
	TD_clock_
	PLL
	PLL
	TD_clock			VGA data
	(27Mhz)		VGA	VGA data
	(27Mhz)	Composite_to_	VGA	VGA multiplexer
		Composite_to_	data(Main)	VGA multiplexer
	TD data	VGA
	TD data	(Main window)
		(Main window)

VGA DAC

Figure 6.3. Block diagram of the TV PIP demonstration.

Demonstration Setup, File Locations, and Instructions

•Project directory: DE2_70_TV_PIP

•Bit stream used: DE2_70_TV_PIP.sof or DE2_70_TV_PIP.pof

•Connect composite video output (yellow plug) of DVD player 1 and DVD player2 to the Video-in 1 and Video-in 2 RCA jack (J8 and J9) of the DE2-70 board respectively. Both DVD players must be configured to provide

o 60 Hz refresh rate o 4:3 aspect ratio

o Non-progressive video

•Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CRT type of monitors should work)

•Connect the one audio output of the DVD player to the line-in port of the DE2-70 board and connect a speaker to the line-out port. If the audio output jacks from the DVD player are of

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Sigma DE2-70 manual Bit stream used DE270TVPIP.sof or DE270TVPIP.pof, Demonstration Setup, File Locations, and Instructions

Contents

Version Copyright 2007 Terasic TechnologiesAltera DE2 Board Chapter 5 Using the DE2-70 BoardChapter 3 DE2-70 Control Panel Chapter 4 DE2-70 Video UtilityChapter 7 Appendix Chapter 6 Examples of Advanced DemonstrationsAltera DE2 Board DE2-70 Package 1.1 Package ContentsChapter DE2-70 User Manual1.2 The DE2-70 Board Assembly Terasic Technologies No. 356, Sec. 1, Fusing E. Rd 1.3 Getting HelpAltera Corporation 101 Innovation Drive San Jose, California, 95134 USA Email university@altera.com2.1 Layout and Components Altera DE2-70 BoardChapter 2.2 Block Diagram of the DE2-70 Board Cyclone II 2C70 FPGA Serial Configuration device and USB Blaster circuitToggle switches Pushbutton switchesSSRAM SDRAMVGA output Audio CODECNTSC/PAL/ SECAM TV decoder circuit 10/100 Ethernet controllerSerial ports 2.3 Power-up the DE2-70 BoardIrDA transceiver Two 40-pin expansion headersThe LCD display shows Welcome to the Altera DE2-70 DE2-70 Control Panel 3.1 Control Panel SetupChapter Figure 3.1. The DE2-70 Control Panel 3.2 Controlling the LEDs, 7-Segment Displays and LCD Display Figure 3.4. Controlling 7-SEG display Figure 3.3. Controlling LEDsDE2-70 User Manual 3.3 Switches and Buttons 3.4 SDRAM/SSRAM/Flash Controller and Programmer Figure 3.7. Accessing the SDRAM-U1 3.5 USB Monitoring 3. Press Load Memory Content to a File button3.6 PS2 Device 3.7 SD CARD 3.8 Audio Playing and Recording Figure 3.11. Playing audio from a selected wave file 3.9 Overall Structure of the DE2-70 Control Panel DE2-70 User Manual Figure 3.13. The block diagram of the DE2-70 control panelFPGA/ SOPC DE2-70 Video Utility 4.1 Video Utility SetupChapter 4.2 VGA Display 4.3 Video Capture 4.4 Overall Structure of the DE2-70 Video Utility Figure 4.4. Video Capture Block Diagram 5.1 Configuring the Cyclone II FPGA Using the DE2-70 BoardChapter Configuring the EPCS16 in AS Mode Configuring the FPGA in JTAG ModeFPGA 5.2 Using the LEDs and Switches Figure 5.4. Schematic diagram of the pushbutton and toggle switches Signal Name Figure 5.5. Schematic diagram of the LEDsDE2-70 User Manual FPGA Pin NoTable 5.2. Pin assignments for the pushbutton switches Table 5.1. Pin assignments for the toggle switchesDE2-70 User Manual 5.3 Using the 7-segment Displays DE2-70 User Manual 5.4 Clock Circuitry Connector Figure 5.8. Block diagram of the clock distributionTable 5.5. Pin assignments for the clock inputs DE2-70 User Manual16 DIGIT LCD 5.5 Using the LCD Module5.6 Using the Expansion Header protection registors and diodes not shown for other ports protection registors and diodes not shown for other portsDE2-70 User Manual 1.8V 2.5VDE2-70 User Manual DE2-70 User Manual Table 5.8. Pin assignments for the expansion headers5.7 Using VGA Figure 5.13. VGA horizontal timing specification DE2-70 User Manual Table 5.11. ADV7123 pin assignments5.8 Using the 24-bit Audio CODEC 5.10 PS/2 Serial Port 5.9 RS-232 Serial Port5.11 Fast Ethernet Network Controller DE2-70 User Manual Figure 5.17. Fast Ethernet schematic5.12 TV Decoder DE2-70 User Manual Figure 5.18. TV Decoder schematic5.13 Implementing a TV Encoder 5.14 Using USB Host and Device http//techtrain.microchip.com/webseminars/documents/IrDABW.pdf 5.15 Using IrDA5.16 Using SDRAM/SRAM/Flash DE2-70 User Manual Figure 5.22. SDRAM schematicSDRAM0 SDRAM1Figure 5.24. Flash schematic Figure 5.23. SSRAM schematicDE2-70 User Manual SSRAM 512Kx36DRAM0A0 DE2-70 User ManualDRAM0CKE DE2-70 User ManualDE2-70 User Manual Table 5.19. SDRAM pin assignmentsSRAM Controller Address Status DE2-70 User ManualSRAM Processor Address Status SRAM Burst Address AdvanceDE2-70 User Manual Table 5.20. SSRAM pin assignmentsDE2-70 User Manual Table 5.21. Flash pin assignmentsInstalling the Demonstrations 6.1 DE2-70 Factory ConfigurationDemonstration Setup, File Locations, and Instructions Bit stream used DE270Default.sof or DE270Default.pof6.2 TV Box Demonstration monitor Figure 6.1. Block diagram of the TV box demonstrationBit stream used DE270TV.sof or DE270TV.pof Demonstration Setup, File Locations, and Instructions6.3 TV Box Picture in Picture PIP Demonstration Demonstration Setup, File Locations, and Instructions Bit stream used DE270TVPIP.sof or DE270TVPIP.pofsignal PiPpositionLoad the bit stream into FPGA 6.4 USB Paintbrush Bit stream used DE270NIOSHOSTMOUSEVGA.sof Project directory DE270NIOSHOSTMOUSEVGANios II Workspace DE270NIOSHOSTMOUSEVGA\Software Demonstration Setup, File Locations, and Instructions6.5 USB Device Bit stream used DE270NIOSDEVICELED.sof Project directory DE270NIOSDEVICELED\HWNios II Workspace DE270NIOSDEVICELED\HW\Software Demonstration Setup, File Locations, and Instructions6.6 A Karaoke Machine Demonstration Setup, File Locations, and Instructions Bit stream used DE2-70i2sound.sof or DE2-70i2sound.pofFigure 6.9. Block diagram of the Karaoke Machine demonstration MP3/Any Audio Output Speaker Microphone 6.7 Ethernet Packet Sending/ReceivingClock/Data Frequency Generator Demonstration Setup, File Locations, and Instructions 6.8 SD Card Music Player Figure 6.13. Block diagram of the SD music player demonstration Bit stream used DE270SDCardAudioPlayer.sof Project directory DE270SDCardAudioPlayerNios II Workspace DE270SDCardAudioPlayer\Software Demonstration Setup, File Locations, and Instructions6.9 Music Synthesizer Demonstration Figure 6.17 illustrates the setup for this demonstration Demonstration Setup, File Locations, and InstructionsBit stream used DE270Synthesizer.sof or DE2-70Synthesizer.pof Speaker Line OutVGALCD/CRTMonitor VGA Out Keyboard Input6.10 Audio Recording and Playing Software Project directory DE270AUDIO\software\projectaudio SOPCDemonstration Setup, File Locations, and Instructions Load the Software Execution File into FPGA. note *1 Revision History AppendixCopyright Statement Chapter