V_VCC33
2
J8
VGND
VGND |
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1 |
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D83 |
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BAT54S | |
3 |
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R89 | 36 |
R90 | 39 |
C26 | 0.1u |
TD1_RESET_n |
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C27 | 0.1u | C28 |
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C29 | 0.1u | 0.1u |
| 28MHZ | |
V_VCC33
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| V_VCC18 | AV1_VCC18 | PV1_VCC18 |
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| TD1_D[0..7] | |||||
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| 14 36 |
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| 27 20 |
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| C31 | 0.1u |
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| U11 | 1 4 |
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| C30 |
| R91 | |||||
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23 |
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| DVDD DVDD |
| DVDDIO DVDDIO | AVDD DD PV |
| 19 | 10n |
| 1.74K | |
AIN1 |
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| ELPF | RN44 | 47 |
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29 |
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AIN2 |
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30 |
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| P0 | 17 | 1 |
| 16 TD1_D0 | ||
AIN3 |
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| 16 | 2 |
| 15 TD1_D1 | |||
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| P1 |
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31 | RESET |
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| 10 | 3 |
| 14 TD1_D2 | |||
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| P2 |
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| 9 | 4 |
| 13 TD1_D3 | ||||
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| P3 |
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26 |
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| 8 | 5 |
| 12 | TD1_D4 | |
VREFN |
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| P4 |
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| 7 | 6 |
| 11 TD1_D5 | ||||
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| P5 |
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| 6 | 7 |
| 10 | TD1_D6 | |
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| P6 |
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25 | VREFP |
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| 5 | 8 |
| 9 | TD1_D7 | ||
| ADV7180 | P7 |
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13 |
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XTAL |
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| 37 | R92 |
| 120 | TD1_VS | ||
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| VS/FIELD |
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12 |
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| 39 | R93 |
| 120 | TD1_HS | ||
XTAL1 |
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| HS |
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| 2 |
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| SFL |
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I2C ADDRESS IS 0x40
V_VCC33
I2C_SCLK
I2C_SDAT
32 | ALSB |
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| 38 |
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| INTRQ |
| TD1_CLK27 | |||
18 |
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| 11 |
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PWRDWN |
| LLC |
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34 |
| 22 |
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SCLK | TEST_0 |
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33 |
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SDATA |
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| ND ND ND ND SEDEXPO ND ND ND DG DG DG DG AG AG AG |
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315354041212428
VGND
V_VCC33 | VGND |
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2 | 1 |
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| D84 |
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| BAT54S | ||
J9 | 3 |
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R94 | 36 | ||
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RCA JACK | R95 | 39 | |
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VGND |
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C32 | 0.1u |
TD2_RESET_n | ||
C33 | 0.1u | C34 |
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C35 | 0.1u | 0.1u |
| 28MHZ | |
23
29
30 31
26
25 13
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| V_VCC33 |
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| TD2_D[0..7] | ||
| V_VCC18 | AV2_VCC18 |
| PV2_VCC18 |
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| 14 36 |
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| 27 20 |
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| C37 | 0.1u |
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U12 | 1 4 |
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| C36 |
| R96 | |||||
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| DVDD DVDD |
| VDDIO DVDDIO D | AVDD PVDD |
| 19 | 10n |
| 1.74K | |
AIN1 |
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| ELPF | RN45 | 47 |
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AIN2 |
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| 17 | TD2_D0 | ||||||
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| P0 | 1 |
| 16 | |||
AIN3 |
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| 16 | 2 |
| 15 | TD2_D1 | ||
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| P1 |
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| 10 | 3 |
| 14 | TD2_D2 | |
RESET |
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| P2 |
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| 9 | 4 |
| 13 | TD2_D3 | |||
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| P3 |
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| 8 | 5 |
| 12 | TD2_D4 | |
VREFN |
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| P4 |
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| 7 | 6 |
| 11 | TD2_D5 | |||
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| P5 |
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| 6 | 7 |
| 10 | TD2_D6 | |
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| P6 |
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| 5 | 8 |
| 9 | TD2_D7 | |
VREFP |
| ADV7180 | P7 |
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XTAL |
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| VS/FIELD | 37 | R97 |
| 120 | TD2_VS | ||
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I2C ADDRESS IS 0x42 | V_VCC33 |
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I2C_SCLK
I2C_SDAT
12 32
18
34 33
XTAL1 |
| HS | 39 | R98 | 120 TD2_HS | |||||
| 2 |
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| SFL |
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ALSB |
| 38 |
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| INTRQ |
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| TD2_CLK27 | ||||
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| 11 |
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PWRDWN |
| LLC |
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| 22 |
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SCLK | TEST_0 |
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SDATA |
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ND ND ND ND SEDEXPO ND ND ND DG DG DG DG AG AG AG |
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315354041212428
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| VGND |
| Figure 5.18. TV Decoder schematic. | |
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Signal Name | FPGA Pin No. | Description |
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TD1_D[0] | PIN_A6 | TV Decoder 1 Data[0] |
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TD1_D[1] | PIN_B6 | TV Decoder 1 Data[1] |
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TD1_D[2] | PIN_A5 | TV Decoder 1 Data[2] |
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TD1_D[3] | PIN_B5 | TV Decoder 1 Data[3] |
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TD1_D[4] | PIN_B4 | TV Decoder 1 Data[4] |
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TD1_D[5] | PIN_C4 | TV Decoder 1 Data[5] |
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TD1_D[6] | PIN_A3 | TV Decoder 1 Data[6] |
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TD1_D[7] | PIN_B3 | TV Decoder 1 Data[7] |
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TD1_HS | PIN_E13 | TV Decoder 1 H_SYNC |
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TD1_VS | PIN_E14 | TV Decoder 1 V_SYNC |
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53
