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Ethernet Media Access Controller (EMAC) Registers
5.40 Receive Pause Timer Register (RXPAUSE)
The receive pause timer register (RXPAUSE) is shown in Figure 66 and described in Table 65.
| Figure 66. Receive Pause Timer Register (RXPAUSE) |
31 | 16 |
| Reserved |
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15 | 0 |
PAUSETIMER
LEGEND: R = Read only;
Table 65. Receive Pause Timer Register (RXPAUSE) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
PAUSETIMER | Receive pause timer value. These bits allow the contents of the receive pause timer to be | ||
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| observed. The receive pause timer is loaded with FF00h when the EMAC sends an outgoing pause |
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| frame (with pause time of FFFFh). The receive pause timer is decremented at slot time intervals. If |
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| the receive pause timer decrements to 0, then another outgoing pause frame is sent and the |
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| load/decrement process is repeated. |
5.41 Transmit Pause Timer Register (TXPAUSE)
The transmit pause timer register (TXPAUSE) is shown in Figure 67 and described in Table 66.
| Figure 67. Transmit Pause Timer Register (TXPAUSE) |
31 | 16 |
| Reserved |
| |
15 | 0 |
PAUSETIMER
LEGEND: R = Read only;
Table 66. Transmit Pause Timer Register (TXPAUSE) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
PAUSETIMER | Transmit pause timer value. These bits allow the contents of the transmit pause timer to be | ||
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| observed. The transmit pause timer is loaded by a received (incoming) pause frame, and then |
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| decremented at slot time intervals down to 0, at which time EMAC transmit frames are again |
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| enabled. |
SPRU941A
Submit Documentation Feedback | Management Data Input/Output (MDIO) |
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