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Ethernet Media Access Controller (EMAC) Registers

5.47 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 73 and described in Table 72.

 

Figure 73. Transmit Channel n Completion Pointer Register (TXnCP)

31

16

 

TXnCP

 

R/W-x

15

0

 

TXnCP

R/W-x

LEGEND: R/W = Read/Write; -n= value after reset; -x = value is indeterminate after reset

Table 72. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions

Bit

Field

Value

Description

31-0

TXnCP

0-FFFF FFFFh

Transmit channel n completion pointer register is written by the host with the buffer descriptor

 

 

 

address for the last buffer processed by the host during interrupt processing. The EMAC uses the

 

 

 

value written to determine if the interrupt should be deasserted.

5.48 Receive Channel 0-7 Completion Pointer Register (RXnCP)

The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 74 and described in Table 73.

 

Figure 74. Receive Channel n Completion Pointer Register (RXnCP)

31

16

 

RXnCP

 

R/W-x

15

0

 

RXnCP

R/W-x

LEGEND: R/W = Read/Write; -n= value after reset; -x = value is indeterminate after reset

Table 73. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions

Bit

Field

Value

Description

31-0

RXnCP

0-FFFF FFFFh

Receive channel n completion pointer register is written by the host with the buffer descriptor

 

 

 

address for the last buffer processed by the host during interrupt processing. The EMAC uses the

 

 

 

value written to determine if the interrupt should be deasserted.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 107

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Texas Instruments TMS320DM643X DMP manual Transmit Channel 0-7 Completion Pointer Register TXnCP