Texas Instruments TMS320DM643X DMP specification

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Ethernet Media Access Controller (EMAC) Registers

5.47 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 73 and described in Table 72.

	Figure 73. Transmit Channel n Completion Pointer Register (TXnCP)
31	16
	TXnCP
	R/W-x
15	0
	TXnCP

R/W-x

LEGEND: R/W = Read/Write; -n= value after reset; -x = value is indeterminate after reset

Table 72. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions

Bit	Field	Value	Description
31-0	TXnCP	0-FFFF FFFFh	Transmit channel n completion pointer register is written by the host with the buffer descriptor
			address for the last buffer processed by the host during interrupt processing. The EMAC uses the
			value written to determine if the interrupt should be deasserted.

5.48 Receive Channel 0-7 Completion Pointer Register (RXnCP)

The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 74 and described in Table 73.

	Figure 74. Receive Channel n Completion Pointer Register (RXnCP)
31	16
	RXnCP
	R/W-x
15	0
	RXnCP

R/W-x

LEGEND: R/W = Read/Write; -n= value after reset; -x = value is indeterminate after reset

Table 73. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions

Bit	Field	Value	Description
31-0	RXnCP	0-FFFF FFFFh	Receive channel n completion pointer register is written by the host with the buffer descriptor
			address for the last buffer processed by the host during interrupt processing. The EMAC uses the
			value written to determine if the interrupt should be deasserted.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 107

Submit Documentation Feedback	Management Data Input/Output (MDIO)

Image 107

Texas Instruments TMS320DM643X DMP manual Transmit Channel 0-7 Completion Pointer Register TXnCP

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Memory Map Signal DescriptionsIndustry Standards Compliance Statement Clock Control Signal Type Description Emac and Mdio Signals Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame Description Packet Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Typical Descriptor Linked List Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format #define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror Flag Bus Arbiter Emac Control ModuleNo Match Nomatch Flag Internal Memory Mdio Module Components Mdio ModuleInterrupt Control Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State Monitoring Mdio Module Operational Overview Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Receive Fifo Emac ModuleEmac Module Components Receive DMA Engine MAC Transmitter Clock and Reset LogicTransmit DMA Engine Transmit Fifo Receive Inter-Frame Interval Media Independent Interface MIIData Reception Receive Control Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Interpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APO Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive Address Matching Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Enabling Receive Channel Teardown Hardware Receive QOS SupportHost Free Buffer Tracking Receive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Receive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit Latency Transfer Node Priority Reset ConsiderationsSoftware Reset Considerations Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO Peripheral Example 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Proper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Emulation Control Power ManagementEmulation Considerations Bit Field Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Acronym Register Description Emac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions No Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Bit Field Value Description Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac Registers Network Statistics Registers Offset Acronym Register Description Transmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear Hostpend Statpend Rxpend Txpend MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Userint Linkint RX7PEND Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked RX7MASK Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Hostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Statmask Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Frames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Reserved RX nFLOWTHRESH FFh Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Loopback Sent. Full-duplex mode no outgoing pause frames are sent MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Bit Field Value Description MAC Status Register Macstatus Field Descriptions Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field Descriptions Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field Descriptions MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloMAC Address High Bytes Register Macaddrhi Macindex MAC Index Register MacindexMAC Index Register Macindex Field Descriptions TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Multicast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register Rxpauseframes Filtered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Good Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register Txpauseframes Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Reference Additions/Modifications/Deletions Table B-1. Document Revision History DSP Products Applications