Texas Instruments TMS320DM643X DMP manual Example 4. Emac Control Module Initialization Code

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Peripheral Architecture

Example 4. EMAC Control Module Initialization Code

Uint32 tmpval ; /*

//Globally disable EMAC/MDIO interrupts in the control module

*/

CSL_FINST( ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ) ;

/* Wait about 100 cycles */ for( I=0; i<5; I++ )

tmpval = ECTL_REGS->EWCTL ;

/* Set Interrupt Timer Count (PLL1clk/6) */ ECTL_REGS->EWINTTCNT = 1500 ;

/*

// Initialize MDIO and EMAC Module

*/[Discussed later in this document]

/* Enable global interrupt in the control module */

CSL_FINST( ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, ENABLE ) ;

2.15.3MDIO Module Initialization

The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE

802.3standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure the clock divider. To set the clock divider, supply an MDIO clock of 1 MHZ. For example, since the base clock used is the peripheral clock (PLL1/6), for a processor operating at a PLL frequency of 594 MHZ the divider can be set to 99, with slower MDIO clocks for slower peripheral clock frequencies being perfectly acceptable.

Both the state machine enable and the MDIO clock divider are controlled through the MDIO control register (CONTROL). If none of the potentially connected PHYs require the access preamble, the PREAMBLE bit in CONTROL can also be set to speed up PHY register access. The code for this may appear as in Example 5.

Example 5. MDIO Module Initialization Code

#define PCLK 99

...

/* Enable MDIO and setup divider */

MDIO_REGS->CONTROL = CSL_FMKT( MDIO_CONTROL_ENABLE, YES) CSL_FMK( MDIO_CONTROL_CLKDIV, PCLK ) ;

If the MDIO module is to operate on an interrupt basis, the interrupts can be enabled at this time using the MDIO user command complete interrupt mask set register (USERINTMASKSET) for register access and the MDIO user PHY select register (USERPHYSELn) if a target PHY is already known.

Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses on the MDIO bus, looking for an active PHY. Since it can take up to 50 μs to read one register, it can be some time before the MDIO module provides an accurate representation of whether a PHY is available. Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling.

For more information on PHY control registers, see your PHY device documentation.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 47

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