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Ethernet Media Access Controller (EMAC) Registers

5.22 Receive Unicast Clear Register (RXUNICASTCLEAR)

The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 48 and described in Table 47.

 

 

Figure 48. Receive Unicast Clear Register (RXUNICASTCLEAR)

 

31

 

 

 

 

 

 

16

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

15

 

 

 

 

 

 

8

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

7

6

5

4

3

2

1

0

RXCH7EN

RXCH6EN

RXCH5EN

RXCH4EN

RXCH3EN

RXCH2EN

RXCH1EN

RXCH0EN

R/WC-0

R/WC-0

R/WC-0

R/WC-0

R/WC-0

R/WC-0

R/WC-0

R/WC-0

LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear, write of 0 has no effect; -n= value after reset

Table 47. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

Bit

Field

Value

Description

31-8

Reserved

0

Reserved

7

RXCH7EN

0-1

Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

6

RXCH6EN

0-1

Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

5

RXCH5EN

0-1

Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

4

RXCH4EN

0-1

Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

3

RXCH3EN

0-1

Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

2

RXCH2EN

0-1

Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

1

RXCH1EN

0-1

Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

0

RXCH0EN

0-1

Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

90 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)

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Texas Instruments TMS320DM643X DMP manual Receive Unicast Clear Register Rxunicastclear