Texas Instruments TMS320DM643X DMP manual

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Ethernet Media Access Controller (EMAC) Registers

5.22 Receive Unicast Clear Register (RXUNICASTCLEAR)

The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 48 and described in Table 47.

		Figure 48. Receive Unicast Clear Register (RXUNICASTCLEAR)
31							16
			Reserved
				R-0
15							8
			Reserved
				R-0
7	6	5	4	3	2	1	0
RXCH7EN	RXCH6EN	RXCH5EN	RXCH4EN	RXCH3EN	RXCH2EN	RXCH1EN	RXCH0EN
R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0	R/WC-0

LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear, write of 0 has no effect; -n= value after reset

Table 47. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

Bit	Field	Value	Description
31-8	Reserved	0	Reserved
7	RXCH7EN	0-1	Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
6	RXCH6EN	0-1	Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
5	RXCH5EN	0-1	Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
4	RXCH4EN	0-1	Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
3	RXCH3EN	0-1	Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
2	RXCH2EN	0-1	Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
1	RXCH1EN	0-1	Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
0	RXCH0EN	0-1	Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

90 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

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Texas Instruments TMS320DM643X DMP manual Receive Unicast Clear Register Rxunicastclear

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix B List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Clock Control Signal DescriptionsIndustry Standards Compliance Statement Memory Map Emac and Mdio Signals Signal Type Description Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Buffer Offset Next Descriptor PointerBuffer Pointer Buffer Length End of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format #define Emacdscflagjabber Buffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber Flag Internal Memory Emac Control ModuleNo Match Nomatch Flag Bus Arbiter Mdio Module Interrupt ControlMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Receive DMA Engine Emac ModuleEmac Module Components Receive Fifo Transmit Fifo Clock and Reset LogicTransmit DMA Engine MAC Transmitter Receive Control Media Independent Interface MIIData Reception Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Adaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address Matching Hardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame Classification Receive Frame Treatment Summary Receive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel Teardown Reset Considerations Software Reset ConsiderationsTransfer Node Priority Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt Link Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt Processing Power Management Emulation ConsiderationsEmulation Control Acronym Register Description Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Bit Field Emac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field Descriptions No Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Phyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Bit Field Value Description Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear Userint Linkint MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Hostpend Statpend Rxpend Txpend Receive Interrupt Status Unmasked Register Rxintstatraw RX7PEND Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset RX7MASK Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Rxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Sent. Full-duplex mode no outgoing pause frames are sent Loopback MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Field Descriptions Bit Field Value Description Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Broadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register Rxoversized Receive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register Txdeferred Transmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term Definition Table B-1. Document Revision History Reference Additions/Modifications/Deletions Products Applications DSP