www.ti.com

Ethernet Media Access Controller (EMAC) Registers

5.11 MAC Input Vector Register (MACINVECTOR)

The MAC input vector register (MACINVECTOR) is shown in Figure 37 and described in Table 36.

Figure 37. MAC Input Vector Register (MACINVECTOR)

31

30

29

 

18

17

16

USERINT

LINKINT

 

Reserved

 

HOSTPEND

STATPEND

R-0

R-0

 

R-0

 

R-0

R-0

15

 

8

7

 

 

0

 

 

RXPEND

 

TXPEND

 

 

 

 

R-0

 

R-0

 

 

LEGEND: R = Read only; -n= value after reset

Table 36. MAC Input Vector Register (MACINVECTOR) Field Descriptions

Bit

Field

Value

Description

31

USERINT

0-1

MDIO module user interrupt (USERINT) pending status bit.

30

LINKINT

0-1

MDIO module link change interrupt (LINKINT) pending status bit.

29-18

Reserved

0

Reserved

17

HOSTPEND

0-1

EMAC module host error interrupt (HOSTPEND) pending status bit.

16

STATPEND

0-1

EMAC module statistics interrupt (STATPEND) pending status bit.

15-8

RXPEND

0-FFh

Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 8 is receive channel 0.

7-0

TXPEND

0-FFh

Transmit channels 0-7 interrupt (TXnPEND) pending status bit. Bit 0 is transmit channel 0.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 79

Submit Documentation Feedback

Management Data Input/Output (MDIO)

 

Page 79
Image 79
Texas Instruments TMS320DM643X DMP MAC Input Vector Register Macinvector, Userint Linkint, Hostpend Statpend Rxpend Txpend