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Ethernet Media Access Controller (EMAC) Registers
5.11 MAC Input Vector Register (MACINVECTOR)
The MAC input vector register (MACINVECTOR) is shown in Figure 37 and described in Table 36.
Figure 37. MAC Input Vector Register (MACINVECTOR)
31 | 30 | 29 |
| 18 | 17 | 16 |
USERINT | LINKINT |
| Reserved |
| HOSTPEND | STATPEND |
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15 |
| 8 | 7 |
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| 0 |
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| RXPEND |
| TXPEND |
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LEGEND: R = Read only;
Table 36. MAC Input Vector Register (MACINVECTOR) Field Descriptions
Bit | Field | Value | Description |
31 | USERINT | MDIO module user interrupt (USERINT) pending status bit. | |
30 | LINKINT | MDIO module link change interrupt (LINKINT) pending status bit. | |
Reserved | 0 | Reserved | |
17 | HOSTPEND | EMAC module host error interrupt (HOSTPEND) pending status bit. | |
16 | STATPEND | EMAC module statistics interrupt (STATPEND) pending status bit. | |
RXPEND | Receive channels | ||
TXPEND | Transmit channels |
SPRU941A
Submit Documentation Feedback | Management Data Input/Output (MDIO) |
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