Texas Instruments TMS320DM643X DMP manual Example of Mdio Register Access Code

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Peripheral Architecture

2.7.2.4Example of MDIO Register Access Code

The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros:

∙PHYREG_read( regadr, phyadr )

∙PHYREG_write( regadr, phyadr, data )

∙PHYREG_wait( )

∙PHYREG_waitResults( results )

Start the process of reading a PHY register

Start the process of writing a PHY register

Synchronize operation (make sure read/write is idle)

Wait for read to complete and return data read

Note that it is not necessary to wait after a write operation, as long as the status is checked before every operation to make sure the MDIO hardware is idle. An alternative approach is to call PHYREG_wait() after every write, and PHYREG_waitResults( ) after every read, then the hardware can be assumed to be idle when starting a new operation.

The implementation of these macros using the chip support library (CSL) is shown in Example 3 (USERACCESS0 is assumed).

Note that this implementation does not check the ACK bit in USERACCESSn on PHY register reads (does not follow the procedure outlined in Section 2.7.2.3). Since the MDIO PHY alive status register (ALIVE) is used to initially select a PHY, it is assumed that the PHY is acknowledging read operations. It is possible that a PHY could become inactive at a future point in time. An example of this would be a PHY that can have its MDIO addresses changed while the system is running. It is not very likely, but this condition can be tested by periodically checking the PHY state in ALIVE.

Example 3. MDIO Register Access Macros

#define PHYREG_read(regadr, phyadr)
MDIO_REGS->USERACCESS0 =
CSL_FMK(MDIO_USERACCESS0_GO,1u)	/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)	/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)
#define PHYREG_write(regadr, phyadr, data)
MDIO_REGS->USERACCESS0 =
CSL_FMK(MDIO_USERACCESS0_GO,1u)	/
CSL_FMK(MDIO_USERACCESS0_WRITE,1)	/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)	/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)	/
CSL_FMK(MDIO_USERACCESS0_DATA, data)

#define PHYREG_wait()

while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) )

#define PHYREG_waitResults( results ) {

while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); }

32 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

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