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Ethernet Media Access Controller (EMAC) Registers
5.28 MAC Control Register (MACCONTROL)
The MAC control register (MACCONTROL) is shown in Figure 54 and described in Table 53.
Figure 54. MAC Control Register (MACCONTROL)
31 |
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| 16 |
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| Reserved |
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15 |
| 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | RXOFFLENBLOCK | RXOWNERSHIP | Reserved | CMDIDLE | Reserved | TXPTYPE | Reserved | |
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7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Reserved | TXPACE | GMIIEN | TXFLOWEN | RXBUFFERFLOWEN | Reserved | LOOPBACK | FULLDUPLEX | |
LEGEND: R = Read only; R/W = Read/Write;
Table 53. MAC Control Register (MACCONTROL) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
14 | RXOFFLENBLOCK |
| Receive offset / length word write block |
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| 0 | Do not block the DMA writes to the receive buffer descriptor offset / buffer length word. |
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| 1 | Block all EMAC DMA controller writes to the receive buffer descriptor offset / buffer length |
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| words during packet processing. When this bit is set, the EMAC will never write the third word |
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| to any receive buffer descriptor. |
13 | RXOWNERSHIP |
| Receive ownership write bit value |
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| 0 | The EMAC writes the Receive ownership bit to 0 at the end of packet processing. |
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| 1 | The EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not |
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| use the ownership mechanism, you can set this mode to preclude the necessity of software |
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| having to set this bit each time the buffer descriptor is used. |
12 | Reserved | 0 | Reserved |
11 | CMDIDLE |
| Command Idle bit |
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| 0 | Idle not commanded |
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| 1 | Idle commanded (read IDLE in the MACSTATUS register) |
10 | Reserved | 0 | Reserved |
9 | TXPTYPE |
| Transmit queue priority type |
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| 0 | The queue uses a |
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| 1 | The queue uses a |
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| for transmission. |
Reserved | 0 | Reserved | |
6 | TXPACE |
| Transmit pacing enable bit |
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| 0 | Transmit pacing is disabled. |
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| 1 | Transmit pacing is enabled. |
5 | GMIIEN |
| GMII enable bit |
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| 0 | GMII RX and TX are held in reset. |
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| 1 | GMII RX and TX are enabled for receive and transmit. |
4 | TXFLOWEN |
| Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon |
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| in |
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| regardless of this bit setting. The RXMBPENABLE bits determine whether or not received |
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| pause frames are transferred to memory. |
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| 0 | Transmit flow control is disabled. |
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| upon. |
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| 1 | Transmit flow control is enabled. |
94 Ethernet Media Access Controller (EMAC)/SPRU941A
Management Data Input/Output (MDIO) | Submit Documentation Feedback |
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