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Ethernet Media Access Controller (EMAC) Registers
5.9Transmit Interrupt Mask Set Register (TXINTMASKSET)
The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 35 and described in Table 34.
| Figure 35. Transmit Interrupt Mask Set Register (TXINTMASKSET) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX7MASK | TX6MASK | TX5MASK | TX4MASK | TX3MASK | TX2MASK | TX1MASK | TX0MASK |
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LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set, write of 0 has no effect;
Table 34. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | TX7MASK | Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
6 | TX6MASK | Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
5 | TX5MASK | Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
4 | TX4MASK | Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
3 | TX3MASK | Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
2 | TX2MASK | Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
1 | TX1MASK | Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
0 | TX0MASK | Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. |
SPRU941A
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