Texas Instruments TMS320DM643X DMP manual Packet Transmit Operation, Receive and Transmit Latency

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Peripheral Architecture

2.11 Packet Transmit Operation

The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7.

2.11.1Transmit DMA Host Configuration

To configure the transmit DMA for operation the host must perform:

∙Write the MAC source address low bytes register (MACSRCADDRLO) and the MAC source address high bytes register (MACSRCADDRHI) (used for pause frames on transmit).

∙Initialize the transmit channel n DMA head descriptor pointer registers (TXnHDP) to 0.

∙Enable the desired transmit interrupts using the transmit interrupt mask set register (TXINTMASKSET) and the transmit interrupt mask clear register (TXINTMASKCLEAR).

∙Set the appropriate configuration bits in the MAC control register (MACCONTROL).

∙Setup the transmit channel(s) buffer descriptors in host memory.

∙Enable the transmit DMA controller by setting the TXEN bit in the transmit control register (TXCONTROL).

∙Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations.

2.11.2Transmit Channel Teardown

The host commands a transmit channel teardown by writing the channel number to the transmit teardown register (TXTEARDOWN). When a teardown command is issued to an enabled transmit channel, the following occurs:

∙Any frame currently in transmission completes normally.

∙The TDOWNCMPLT flag is set in the next SOP buffer descriptor in the chain, if there is one.

∙The channel head descriptor pointer is cleared to 0.

∙A transmit interrupt is issued to inform the host of the channel teardown.

∙The corresponding transmit channel n completion pointer register (TXnCP) contains the value FFFF FFFCh.

∙The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value.

Channel teardown may be commanded on any channel at any time. The host is informed of the teardown completion by the set teardown complete (TDOWNCMPLT) buffer descriptor bit. The EMAC does not clear any channel enables due to a teardown command. A teardown command to an inactive channel issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to TXnCP (note that there is no buffer descriptor in this case). Software may read the interrupt acknowledge location (TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command.

2.12 Receive and Transmit Latency

The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a complete packet, are available in the FIFO.

Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less). For larger packet sizes, transmit underrun occurs if the memory latency is greater than the time required to transmit a 64-byte cell on the wire; this is 5.12 μs in 100 Mbps mode and 51.2 μs in 10 Mbps mode. The memory latency time includes all buffer descriptor reads for the entire cell data.

Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire: 5.12 μs in 100 Mbps mode, or 51.2 μs in 10 Mbps mode. The latency time includes any required buffer descriptor reads for the cell data.

44 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

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