MAC Status Register Macstatus | Texas Instruments TMS320DM643X DMP

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Ethernet Media Access Controller (EMAC) Registers

5.29 MAC Status Register (MACSTATUS)

The MAC status register (MACSTATUS) is shown in Figure 55 and described in Table 54.

Figure 55. MAC Status Register (MACSTATUS)

31	30	24	23	20	19	18	16
IDLE	Reserved			TXERRCODE	Rsvd		TXERRCH
R-0	R-0			R-0	R-0		R-0
	15	12	11	10			8
	RXERRCODE		Reserved		RXERRCH
	R-0		R-0			R-0
	7		3	2		1	0
	Reserved			RXQOSACT	RXFLOWACT		TXFLOWACT
	R-0			R-0		R-0	R-0
LEGEND: R = Read only; -n= value after reset

Table 54. MAC Status Register (MACSTATUS) Field Descriptions

Bit	Field	Value	Description
31	IDLE		EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1.
		0	The EMAC is not idle.
		1	The EMAC is in the idle state.
30-24	Reserved	0	Reserved
23-20	TXERRCODE	0-Fh	Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors.
			The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host
			error interrupts require hardware reset in order to recover. A 0 packet length is an error, but it is not
			detected.
		0	No error
		1h	SOP error; the buffer is the first buffer in a packet, but the SOP bit is not set in software.
		2h	Ownership bit not set in SOP buffer
		3h	Zero next buffer descriptor pointer without EOP
		4h	Zero buffer pointer
		5h	Zero buffer length
		6h	Packet length error (sum of buffers is less than packet length)
19	Reserved	0	Reserved
18-16	TXERRCH	0-7h	Transmit host error channel. These bits indicate which transmit channel the host error occurred on.
			This field is cleared to 0 on a host read.
		0	The host error occurred on transmit channel 0
		1h	The host error occurred on transmit channel 1
		2h	The host error occurred on transmit channel 2
		3h	The host error occurred on transmit channel 3
		4h	The host error occurred on transmit channel 4
		5h	The host error occurred on transmit channel 5
		6h	The host error occurred on transmit channel 6
		7h	The host error occurred on transmit channel 7
15-12	RXERRCODE	0-Fh	Receive host error code. These bits indicate that EMAC detected receive DMA related host errors.
			The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host
			error interrupts require hardware reset in order to recover.
		0	No error
		2h	Ownership bit not set in SOP buffer
		4h	Zero buffer pointer
11	Reserved	0	Reserved

96 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)	Submit Documentation Feedback

Image 96

Texas Instruments TMS320DM643X DMP manual MAC Status Register Macstatus Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix B List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Signal Descriptions Industry Standards Compliance StatementClock Control Memory Map Emac and Mdio Signals Signal Type Description Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format #define Emacdscflagjabber Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber Flag Emac Control Module No Match Nomatch FlagInternal Memory Bus Arbiter Mdio Module Interrupt ControlMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo Clock and Reset Logic Transmit DMA EngineTransmit Fifo MAC Transmitter Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame Classification Receive Frame Treatment Summary Receive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel Teardown Reset Considerations Software Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt User Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt Processing Power Management Emulation ConsiderationsEmulation Control Emac Control Module Interrupt Control Register Ewctl Emac Control Module RegistersAcronym Register Description Bit Field Emac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions No Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Bit Field Value Description Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsUserint Linkint Hostpend Statpend Rxpend Txpend Receive Interrupt Status Unmasked Register Rxintstatraw RX7PEND Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset RX7MASK Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask Hostmask Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Sent. Full-duplex mode no outgoing pause frames are sent Loopback MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Field Descriptions Bit Field Value Description Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Network Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term Definition Table B-1. Document Revision History Reference Additions/Modifications/Deletions Products Applications DSP