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| List of Figures |
|
| 1 | EMAC and MDIO Block Diagram | 12 |
| 2 | Typical Ethernet Configuration | 14 |
| 3 | Ethernet Frame Format | 15 |
| 4 | Basic Descriptor Format | 16 |
| 5 | Typical Descriptor Linked List | 17 |
| 6 | Transmit Buffer Descriptor Format | 20 |
| 7 | Receive Buffer Descriptor Format | 23 |
| 8 | EMAC Control Module Block Diagram | 27 |
| 9 | MDIO Module Block Diagram | 29 |
| 10 | EMAC Module Block Diagram | 33 |
| 11 | EMAC Control Module Interrupt Control Register (EWCTL) | 53 |
| 12 | EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) | 54 |
| 13 | MDIO Version Register (VERSION) | 55 |
| 14 | MDIO Control Register (CONTROL) | 56 |
| 15 | PHY Acknowledge Status Register (ALIVE) | 57 |
| 16 | PHY Link Status Register (LINK) | 57 |
| 17 | MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) | 58 |
| 18 | MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) | 59 |
| 19 | MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) | 60 |
| 20 | MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) | 61 |
| 21 | MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) | 62 |
| 22 | MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) | 63 |
| 23 | MDIO User Access Register 0 (USERACCESS0) | 64 |
| 24 | MDIO User PHY Select Register 0 (USERPHYSEL0) | 65 |
| 25 | MDIO User Access Register 1 (USERACCESS1) | 66 |
| 26 | MDIO User PHY Select Register 1 (USERPHYSEL1) | 67 |
| 27 | Transmit Identification and Version Register (TXIDVER) | 71 |
| 28 | Transmit Control Register (TXCONTROL) | 71 |
| 29 | Transmit Teardown Register (TXTEARDOWN) | 72 |
| 30 | Receive Identification and Version Register (RXIDVER) | 73 |
| 31 | Receive Control Register (RXCONTROL) | 73 |
| 32 | Receive Teardown Register (RXTEARDOWN) | 74 |
| 33 | Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) | 75 |
| 34 | Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) | 76 |
| 35 | Transmit Interrupt Mask Set Register (TXINTMASKSET) | 77 |
| 36 | Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) | 78 |
| 37 | MAC Input Vector Register (MACINVECTOR) | 79 |
| 38 | Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) | 80 |
| 39 | Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) | 81 |
| 40 | Receive Interrupt Mask Set Register (RXINTMASKSET) | 82 |
| 41 | Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) | 83 |
| 42 | MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) | 84 |
| 43 | MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) | 84 |
| 44 | MAC Interrupt Mask Set Register (MACINTMASKSET) | 85 |
| 45 | MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) | 85 |
| 46 | Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) | 86 |
| 47 | Receive Unicast Enable Set Register (RXUNICASTSET) | 89 |
| 48 | Receive Unicast Clear Register (RXUNICASTCLEAR) | 90 |
| 49 | Receive Maximum Length Register (RXMAXLEN) | 91 |
| 50 | Receive Buffer Offset Register (RXBUFFEROFFSET) | 91 |
| 51 | Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) | 92 |
| 52 | Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) | 92 |
6 | List of Figures | SPRU941A | |
