Texas Instruments TMS320DM643X DMP manual Emac Control Module Interrupt Control Register Ewctl

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EMAC Control Module Registers

3EMAC Control Module Registers

Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers.

Table 7. EMAC Control Module Registers

Offset	Acronym	Register Description	Section
04h	EWCTL	EMAC Control Module Interrupt Control Register	Section 3.1
08h	EWINTTCNT	EMAC Control Module Interrupt Timer Count Register	Section 3.2

3.1EMAC Control Module Interrupt Control Register (EWCTL)

The EMAC control module interrupt control register (EWCTL) is used to enable and disable the central interrupt from the EMAC and MDIO modules.

It is expected that any time the EMAC and MDIO interrupt is being serviced, the software disables the INTEN bit in EWCTL. This ensures that the interrupt line goes back to zero. The software re-enables the INTEN bit after clearing all the pending interrupts and before leaving the interrupt service routine. At this point, if the EMAC control module monitors any interrupts still pending, it reasserts the interrupt line, and generates a new edge that the CPU can recognize.

Any time the INTEN bit is cleared to 0, the EMAC_MDIO_INT signal to the CPU is kept deasserted. If the INTEN bit is set to 1, then the interrupt control logic checks all the interrupt lines from EMAC and MDIO. If any of these interrupt lines are active, the EMAC_MDIO_INT signal is asserted. Assertion of this signal generates an edge, which can then be recognized as a valid interrupt by the CPU.

The INTEN bit takes care of two problems associated with level interrupts from the EMAC and the MDIO modules. First, it makes sure that none of the interrupts are missed; second, it makes sure that only the required number of interrupts are sent to the CPU.

The EWCTL is shown in Figure 11 and described in Table 8.

Figure 11. EMAC Control Module Interrupt Control Register (EWCTL)

31		16
Reserved
R-0
15	1	0
Reserved		INTEN
R-0		R/W-0

LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 8. EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions

Bit	Field	Value	Description
31-1	Reserved	0	Reserved
0	INTEN		Controls the EMAC_MDIO_INT interrupt generation to the CPU.
		0	EMAC and MDIO interrupts are disabled.
		1	EMAC and MDIO interrupts are enabled.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 53

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