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MDIO Registers
4.9MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 21 and described in Table 19.
Figure 21. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
Reserved |
| USERINTMASKSET | |
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LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set;
Table 19. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
USERINTMASKSET |
| MDIO user interrupt mask set for USERINTMASKED[1:0], respectively. Setting a bit to 1 will | |
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| enable MDIO user command complete interrupts for that particular USERACCESS register. |
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| MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit |
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| is 0. USERINTMASKSET[0] and USERINTMASKSET[1] correspond to USERACCESS0 and |
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| USERACCESS1, respectively. Writing a 0 to this register has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register n |
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| (USERACCESSn) are disabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register n |
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| (USERACCESSn) are enabled. |
62 Ethernet Media Access Controller (EMAC)/SPRU941A
Management Data Input/Output (MDIO) | Submit Documentation Feedback |
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