Soft Reset Register Softreset | Texas Instruments TMS320DM643X DMP

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Ethernet Media Access Controller (EMAC) Registers

5.32 MAC Configuration Register (MACCONFIG)

The MAC configuration register (MACCONFIG) is shown in Figure 58 and described in Table 57.

Figure 58. MAC Configuration Register (MACCONFIG)

31	24	23	16
	TXCELLDEPTH		RXCELLDEPTH
	R-3h		R-3h
15	8	7	0
	ADDRESSTYPE		MACCFIG
	R-1		R-1

LEGEND: R = Read only; -n= value after reset

Table 57. MAC Configuration Register (MACCONFIG) Field Descriptions

Bit	Field	Value	Description
31-24	TXCELLDEPTH	3h	Transmit cell depth. These bits indicate the number of cells in the transmit FIFO.
23-16	RXCELLDEPTH	3h	Receive cell depth. These bits indicate the number of cells in the receive FIFO.
15-8	ADDRESSTYPE	1h	Address type
7-0	MACCFIG	1h	MAC configuration value

5.33 Soft Reset Register (SOFTRESET)

The soft reset register (SOFTRESET) is shown in Figure 59 and described in Table 58.

Figure 59. Soft Reset Register (SOFTRESET)

31		16
Reserved
R-0
15	1	0
Reserved		SOFTRESET
R-0		R/W-0

LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 58. Soft Reset Register (SOFTRESET) Field Descriptions

Bit	Field	Value	Description
31-1	Reserved	0	Reserved
0	SOFTRESET		Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. Software reset occurs
			when the receive and transmit DMA controllers are in an idle state to avoid locking up the
			Configuration bus. After writing a 1 to this bit, it may be polled to determine if the reset has
			occurred. If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred.
		0	A software reset has not occurred.
		1	A software reset has occurred.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 99

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Texas Instruments TMS320DM643X DMP manual MAC Configuration Register Macconfig, Soft Reset Register Softreset

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Memory Map Signal DescriptionsIndustry Standards Compliance Statement Clock Control Signal Type Description Emac and Mdio Signals Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format #define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror Flag Bus Arbiter Emac Control ModuleNo Match Nomatch Flag Internal Memory Mdio Module Interrupt ControlMdio Module Components Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State Monitoring Mdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Receive Fifo Emac ModuleEmac Module Components Receive DMA Engine MAC Transmitter Clock and Reset LogicTransmit DMA Engine Transmit Fifo Receive Inter-Frame Interval Media Independent Interface MIIData Reception Receive Control Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Interpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APO Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive Address Matching Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Enabling Hardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Receive Frame Treatment Summary Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit Latency Reset Considerations Software Reset ConsiderationsTransfer Node Priority Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO Peripheral Example 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Proper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Power Management Emulation ConsiderationsEmulation Control Bit Field Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Acronym Register Description Emac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions No Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Bit Field Value Description Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac Registers Network Statistics Registers Offset Acronym Register Description Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear Hostpend Statpend Rxpend Txpend MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Userint Linkint RX7PEND Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked RX7MASK Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Statmask Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Frames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Reserved RX nFLOWTHRESH FFh Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Loopback Sent. Full-duplex mode no outgoing pause frames are sent MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Bit Field Value Description MAC Status Register Macstatus Field Descriptions Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Multicast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register Rxpauseframes Filtered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register Txpauseframes Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register Txmulticoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Reference Additions/Modifications/Deletions Table B-1. Document Revision History DSP Products Applications