Texas Instruments TMS320DM643X DMP instruction

www.ti.com

MDIO Registers

4.8MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 20 and described in Table 18.

Figure 20. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

31			16
	Reserved
	R-0
15	2	1	0
Reserved		USERINTMASKED
R-0			R/WC-0

LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n= value after reset

Table 18. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1-0	USERINTMASKED		Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
			the previously scheduled PHY read or write command using that particular USERACCESS
			register has completed and the corresponding USERINTMASKSET bit is set to 1.
			USERINTMASKED[0] and USERINTMASKED[1] correspond to USERACCESS0 and
			USERACCESS1, respectively. Writing a 1 will clear the interrupt and writing a 0 has no effect.
		0	No MDIO user command complete event.
		1	The previously scheduled PHY read or write command using MDIO user access register n
			(USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 61

Submit Documentation Feedback	Management Data Input/Output (MDIO)

Image 61

Texas Instruments TMS320DM643X DMP manual USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix a List of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Industry Standards Compliance Statement Signal DescriptionsClock Control Memory Map Signal Type Description Emac and Mdio Signals Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes Description Programming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Typical Descriptor Linked List Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format #define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber Flag No Match Nomatch Flag Emac Control ModuleInternal Memory Bus Arbiter Interrupt Control Mdio ModuleMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Emac Module Components Emac ModuleReceive DMA Engine Receive Fifo Transmit DMA Engine Clock and Reset LogicTransmit Fifo MAC Transmitter Data Reception Media Independent Interface MIIReceive Control Receive Inter-Frame Interval Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control CRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Speed, Duplex, and Pause Frame Support Transmit Flow Control Packet Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address Matching Host Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Receive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Receive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel Teardown Software Reset Considerations Reset ConsiderationsTransfer Node Priority Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Mdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Mdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt Processing Emulation Considerations Power ManagementEmulation Control Emac Control Module Registers Emac Control Module Interrupt Control Register EwctlAcronym Register Description Bit Field Emac Control Module Interrupt Timer Count Register Ewinttcnt Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions No Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Bit Field Value Description Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac Registers Network Statistics Registers Offset Acronym Register Description Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorUserint Linkint Hostpend Statpend Rxpend Txpend RX7PEND Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked RX7MASK Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask Hostmask Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Reserved RX nFLOWTHRESH FFh Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Loopback Sent. Full-duplex mode no outgoing pause frames are sent MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Bit Field Value Description MAC Status Register Macstatus Field Descriptions Fifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions Soft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address High Bytes Register Macaddrhi MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex Field Descriptions MAC Index Register MacindexMacindex TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Good Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer Definitions Reference Additions/Modifications/Deletions Table B-1. Document Revision History DSP Products Applications