Texas Instruments TMS320DM643X DMP manual Initialization, Hardware Reset Considerations

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Peripheral Architecture

2.14.2Hardware Reset Considerations

When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initialized before being able to resume its data transmission, as described in Section 2.15.

A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors. Before doing a hardware reset, you should inspect the error codes in the MAC status register (MACSTATUS) that gives information about the type of software error that needs to be corrected. For detailed information on error interrupts, see Section 2.16.1.4.

2.15 Initialization

2.15.1Enabling the EMAC/MDIO Peripheral

When the device is powered on, the EMAC peripheral is in a disabled state. Before any EMAC specific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be written and the reads will all return a value of zero.

The EMAC/MDIO is enabled through the Power and Sleep Controller (PSC) registers. For information on how to enable the EMAC peripheral from the Power and Sleep Controller, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).

When first enabled, the EMAC peripheral registers are set to their default values. After enabling the peripheral, you may proceed with the module specific initialization.

2.15.2EMAC Control Module Initialization

The EMAC control module is used for global interrupt enable, and to pace back-to-back interrupts using an interrupt retrigger count based on the peripheral clock (PLL1/6). There is also an 8K block of RAM local to the EMAC that is used to hold packet buffer descriptors.

Note that although the EMAC control module and the EMAC module have slightly different functions, in practice, the type of maintenance performed on the EMAC control module is more commonly conducted from the EMAC module software (as opposed to the MDIO module).

The initialization of the EMAC control module consists of two parts:

1.Configuration of the interrupt to the CPU.

2.Initialization of the EMAC control module:

∙Setting the interrupt pace count using the EMAC control module interrupt timer count register (EWINTTCNT).

∙Initializing the EMAC and MDIO modules.

∙Enabling interrupts in the EMAC control module using the EMAC control module interrupt control register (EWCTL).

When using the register-level CSL, the code to perform the actions associated with the second part may appear as in Example 4.

The process of mapping the EMAC interrupts to one of the CPU’s interrupts is done using the DSP interrupt controller. Once the interrupt is mapped to a CPU interrupt, general masking and unmasking of the interrupt (to control reentrancy) should be done at the chip level by manipulating the interrupt enable mask. The EMAC control module interrupt control register (EWCTL) should only be used to enable and disable interrupts from within the EMAC interrupt service routine (ISR). This is because disabling and reenabling the interrupt in EWCTL also resets the interrupt pace counter.

46 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

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