Texas Instruments TMS320DM643X DMP manual PHY Acknowledge Status Register Alive

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MDIO Registers

4.3PHY Acknowledge Status Register (ALIVE)

The PHY acknowledge status register (ALIVE) is shown in Figure 15 and described in Table 13.

	Figure 15. PHY Acknowledge Status Register (ALIVE)
31	16
	ALIVE
	R/WC-0
15	0
	ALIVE

R/WC-0

LEGEND: R/W = Read/Write; WC = Write 1 to clear; -n= value after reset

Table 13. PHY Acknowledge Status Register (ALIVE) Field Descriptions

Bit	Field	Value	Description
31-0	ALIVE		MDIO Alive bits. Each of the 32 bits of this register is set if the most recent access to the PHY with
			address corresponding to the register bit number was acknowledged by the PHY; the bit is reset if the
			PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the
			corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the
			presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0
			has no effect.
		0	The PHY fails to acknowledge the access.

1The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY.

4.4PHY Link Status Register (LINK)

The PHY link status register (LINK) is shown in Figure 16 and described in Table 14.

	Figure 16. PHY Link Status Register (LINK)
31	16
	LINK
	R-0
15	0

LINK

R-0

LEGEND: R = Read only; -n= value after reset

			Table 14. PHY Link Status Register (LINK) Field Descriptions
Bit	Field	Value	Description
31-0	LINK		MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. The bit
			is set if the PHY with the corresponding address has link and the PHY acknowledges the read
			transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read
			transaction. Writes to the register have no effect.
		0	The PHY indicates it does not have a link or fails to acknowledge the read transaction
		1	The PHY with the corresponding address has a link and the PHY acknowledges the read transaction.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 57

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