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Ethernet Media Access Controller (EMAC) Registers
5.8Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 34 and described in Table 33.
| Figure 34. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX7PEND | TX6PEND | TX5PEND | TX4PEND | TX3PEND | TX2PEND | TX1PEND | TX0PEND |
LEGEND: R = Read only;
Table 33. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | TX7PEND | TX7PEND masked interrupt read | |
6 | TX6PEND | TX6PEND masked interrupt read | |
5 | TX5PEND | TX5PEND masked interrupt read | |
4 | TX4PEND | TX4PEND masked interrupt read | |
3 | TX3PEND | TX3PEND masked interrupt read | |
2 | TX2PEND | TX2PEND masked interrupt read | |
1 | TX1PEND | TX1PEND masked interrupt read | |
0 | TX0PEND | TX0PEND masked interrupt read |
76 Ethernet Media Access Controller (EMAC)/SPRU941A
Management Data Input/Output (MDIO) | Submit Documentation Feedback |
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