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TMS320DM643X DMP manual Submit Documentation Feedback
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TMS320DM643X DMP
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Error codes
Functional Block Diagram
Receive DMA Host Configuration
Clock and Reset Logic
Host Error Interrupt
Pausetimer
Signal Descriptions
Power Management
PHY Register User Access
Features
Page 2
Image 2
2
SPRU941A
–April
2007
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Page 1
Page 3
Page 2
Image 2
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Page 3
Contents
Users Guide
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Contents
MAC Hash Address Register 1 MACHASH1
Appendix a
Appendix B
List of Figures
Transmit Pacing Algorithm Test Register Tpacetest
List of Tables
Fifo Control Register Fifocontrol Field Descriptions
Read This First
Features
Purpose of the Peripheral
Functional Block Diagram
Emac and Mdio Block Diagram
Clock Control
Signal Descriptions
Industry Standards Compliance Statement
Memory Map
Emac and Mdio Signals
Signal Type Description
Ethernet Frame Description
Ethernet Protocol Overview
Ethernet Frame Format
Field Bytes Description
Packet Buffer Descriptors
Ethernet’s Multiple Access Protocol
Programming Interface
Basic Descriptor Description
Typical Descriptor Linked List
Transmit and Receive Descriptor Queues
Transmit and Receive Emac Interrupts
Transmit Buffer Descriptor Format
Example 1. Transmit Buffer Descriptor in C Structure Format
Buffer Offset
Next Descriptor Pointer
Buffer Pointer
Buffer Length
End of Queue EOQ Flag
End of Packet EOP Flag
Ownership Owner Flag
Teardown Complete Tdowncmplt Flag
Receive Buffer Descriptor Format
Receive Buffer Descriptor Format
Example 2. Receive Buffer Descriptor in C Structure Format
#define Emacdscflagjabber
Buffer Length
CRC Error Crcerror Flag
Code Error Codeerror Flag
Alignment Error Alignerror Flag
Jabber Flag
Internal Memory
Emac Control Module
No Match Nomatch Flag
Bus Arbiter
Mdio Module Components
Mdio Module
Interrupt Control
Global PHY Detection and Link State Monitoring
PHY Register User Access
Mdio Clock Generator
Active PHY Monitoring
Mdio Module Operational Overview
Reading Data From a PHY Register
Initializing the Mdio Module
Writing Data To a PHY Register
Example of Mdio Register Access Code
Example 3. Mdio Register Access Macros
Receive DMA Engine
Emac Module
Emac Module Components
Receive Fifo
Transmit Fifo
Clock and Reset Logic
Transmit DMA Engine
MAC Transmitter
Receive Control
Media Independent Interface MII
Data Reception
Receive Inter-Frame Interval
Collision-Based Receive Buffer Flow Control
Ieee 802.3x-Based Receive Buffer Flow Control
Adaptive Performance Optimization APO
Transmit Control
CRC Insertion
Interpacket-Gap IPG Enforcement
Transmit Flow Control
Speed, Duplex, and Pause Frame Support
Receive Channel Enabling
Receive DMA Host Configuration
Packet Receive Operation
Receive Address Matching
Receive Channel Teardown
Hardware Receive QOS Support
Host Free Buffer Tracking
Promiscuous Receive Mode
Receive Frame Classification
Receive Frame Treatment Summary
Receive Frame Treatment
Middle of Frame Overrun Treatment
Receive Overrun
Middle of Frame Overrun Treatment
Receive and Transmit Latency
Transmit DMA Host Configuration
Packet Transmit Operation
Transmit Channel Teardown
Transfer Node Priority
Reset Considerations
Software Reset Considerations
Enabling the EMAC/MDIO Peripheral
Hardware Reset Considerations
Initialization
Emac Control Module Initialization
Example 5. Mdio Module Initialization Code
Example 4. Emac Control Module Initialization Code
Mdio Module Initialization
Emac Module Initialization
Transmit Packet Completion Interrupts
Interrupt Support
Emac Module Interrupt Events and Requests
Receive Packet Completion Interrupts
Host Error Interrupt
Statistics Interrupt
Link Change Interrupt
User Access Completion Interrupt
Mdio Module Interrupt Events and Requests
Proper Interrupt Processing
Emulation Control
Power Management
Emulation Considerations
Acronym Register Description
Emac Control Module Interrupt Control Register Ewctl
Emac Control Module Registers
Bit Field
Emac Control Module Interrupt Timer Count Register Ewinttcnt
Mdio Version Register Version Field Descriptions
Mdio Version Register Version
Management Data Input/Output Mdio Registers
Mdio Control Register Control
Mdio Control Register Control Field Descriptions
PHY Acknowledge Status Register Alive Field Descriptions
PHY Acknowledge Status Register Alive
PHY Link Status Register Link
PHY Link Status Register Link Field Descriptions
No Mdio link change event
Will clear the event and writing a 0 has no effect
No Mdio user command complete event
USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0
WS-0
Userintmaskclear
Mdio User Access Register 0 USERACCESS0
Mdio User Access Register 0 USERACCESS0 Field Descriptions
Phyadrmon
Mdio User PHY Select Register 0 USERPHYSEL0
Linksel Linkintenb
Bit Field Value Description
Mdio User Access Register 1 USERACCESS1
Mdio User Access Register 1 USERACCESS1 Field Descriptions
Mdio User PHY Select Register 1 USERPHYSEL1
Mdio User PHY Select Register 1 USERPHYSEL1
Ethernet Media Access Controller Emac Registers
Ethernet Media Access Controller Emac Registers
Offset Acronym Register Description
Offset Acronym Register Description
Network Statistics Registers
Transmit Control Register Txcontrol Field Descriptions
Transmit Identification and Version Register Txidver
Transmit Control Register Txcontrol
Txtdnch
Transmit Teardown Register Txteardown
Transmit Teardown Register Txteardown Field Descriptions
Receive Control Register Rxcontrol Field Descriptions
Receive Identification and Version Register Rxidver
Receive Control Register Rxcontrol
Rxtdnch
Receive Teardown Register Rxteardown
Receive Teardown Register Rxteardown Field Descriptions
Transmit Interrupt Status Unmasked Register Txintstatraw
TX7PEND
Transmit Interrupt Status Masked Register Txintstatmasked
Transmit Interrupt Status Masked Register Txintstatmasked
Transmit Interrupt Mask Set Register Txintmaskset
TX7MASK
Transmit Interrupt Mask Clear Register Txintmaskclear
Transmit Interrupt Mask Clear Register Txintmaskclear
Userint Linkint
MAC Input Vector Register Macinvector
MAC Input Vector Register Macinvector Field Descriptions
Hostpend Statpend Rxpend Txpend
Receive Interrupt Status Unmasked Register Rxintstatraw
RX7PEND
Receive Interrupt Status Masked Register Rxintstatmasked
Receive Interrupt Status Masked Register Rxintstatmasked
Receive Interrupt Mask Set Register Rxintmaskset
RX7MASK
Receive Interrupt Mask Clear Register Rxintmaskclear
Receive Interrupt Mask Clear Register Rxintmaskclear
Hostpend Statpend
MAC Interrupt Status Unmasked Register Macintstatraw
MAC Interrupt Status Masked Register Macintstatmasked
Hostmask Statmask
MAC Interrupt Mask Set Register Macintmaskset
MAC Interrupt Mask Clear Register Macintmaskclear
Hostmask
Rxcsfen Rxcefen Rxcafen
Rxpasscrc Rxqosen Rxnochain
Rxcmfen
Rxpromch
Frames containing errors are filtered
Receive multicast channel select
Receive Unicast Enable Set Register Rxunicastset
RXCH7EN
Receive Unicast Clear Register Rxunicastclear
Receive Unicast Clear Register Rxunicastclear
Receive Maximum Length Register Rxmaxlen Field Descriptions
Receive Maximum Length Register Rxmaxlen
Receive Buffer Offset Register Rxbufferoffset
Rxfilterthresh
Reserved RX nFLOWTHRESH FFh
Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER
MAC Control Register Maccontrol
MAC Control Register Maccontrol Field Descriptions
Sent. Full-duplex mode no outgoing pause frames are sent
Loopback
MAC Status Register Macstatus
MAC Status Register Macstatus Field Descriptions
MAC Status Register Macstatus Field Descriptions
Bit Field Value Description
Emulation Control Register Emcontrol Field Descriptions
Emulation Control Register Emcontrol
Fifo Control Register Fifocontrol
Fifo Control Register Fifocontrol Field Descriptions
MAC Configuration Register Macconfig Field Descriptions
MAC Configuration Register Macconfig
Soft Reset Register Softreset
Soft Reset Register Softreset Field Descriptions
MAC Source Address Low Bytes Register Macsrcaddrlo
MAC Source Address High Bytes Register Macsrcaddrhi
MAC Hash Address Register 1 MACHASH1 Field Descriptions
MAC Hash Address Register 1 MACHASH1
MAC Hash Address Register 2 MACHASH2
MAC Hash Address Register 2 MACHASH2 Field Descriptions
Back Off Test Register Bofftest Field Descriptions
Back Off Test Register Bofftest
Transmit Pacing Algorithm Test Register Tpacetest
Receive Pause Timer Register Rxpause Field Descriptions
Receive Pause Timer Register Rxpause
Transmit Pause Timer Register Txpause
Transmit Pause Timer Register Txpause Field Descriptions
MAC Address Low Bytes Register Macaddrlo Field Descriptions
MAC Address Low Bytes Register Macaddrlo
MAC Address High Bytes Register Macaddrhi
Macindex
MAC Index Register Macindex
MAC Index Register Macindex Field Descriptions
TX nHDP
Transmit Channel 0-7 Completion Pointer Register TXnCP
Receive Channel 0-7 Completion Pointer Register RXnCP
Broadcast Receive Frames Register Rxbcastframes
Network Statistics Registers
Good Receive Frames Register Rxgoodframes
Multicast Receive Frames Register Rxmcastframes
Pause Receive Frames Register Rxpauseframes
Receive CRC Errors Register Rxcrcerrors
Receive Alignment/Code Errors Register Rxaligncodeerrors
Receive Oversized Frames Register Rxoversized
Receive Frame Fragments Register Rxfragments
Receive Jabber Frames Register Rxjabber
Receive Undersized Frames Register Rxundersized
Filtered Receive Frames Register Rxfiltered
Good Transmit Frames Register Txgoodframes
Receive QOS Filtered Frames Register Rxqosfiltered
Receive Octet Frames Register Rxoctets
Pause Transmit Frames Register Txpauseframes
Broadcast Transmit Frames Register Txbcastframes
Multicast Transmit Frames Register Txmcastframes
Deferred Transmit Frames Register Txdeferred
Transmit Multiple Collision Frames Register Txmulticoll
Transmit Underrun Error Register Txunderrun
Transmit Single Collision Frames Register Txsinglecoll
Transmit Late Collision Frames Register Txlatecoll
Transmit and Receive 64 Octet Frames Register FRAME64
Transmit Carrier Sense Errors Register Txcarriersense
Transmit Octet Frames Register Txoctets
Network Octet Frames Register Netoctets
Receive DMA Overruns Register Rxdmaoverruns
Appendix a Glossary
Table A-1. Physical Layer Definitions
Term Definition
Table B-1. Document Revision History
Reference Additions/Modifications/Deletions
Products Applications
DSP