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Texas Instruments TMS320DM643X DMP manual No Mdio user command complete event

Models: TMS320DM643X DMP

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MDIO Registers

4.7MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 19 and described in Table 17.

Figure 19. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

31			16
Reserved
R-0
15	2	1	0
Reserved		USERINTRAW
R-0		R/WC-0

LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n= value after reset

Table 17. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1-0	USERINTRAW		MDIO User command complete event bits. When asserted, a bit indicates that the previously
			scheduled PHY read or write command using that particular USERACCESS register has
			completed. USERINTRAW[0] and USERINTRAW[1] correspond to USERACCESS0 and
			USERACCESS1, respectively. Writing a 1 will clear the event and writing a 0 has no effect.
		0	No MDIO user command complete event.
		1	The previously scheduled PHY read or write command using MDIO user access register n
			(USERACCESSn) has completed.

60 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)	Submit Documentation Feedback

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Texas Instruments TMS320DM643X DMP manual No Mdio user command complete event

Contents

Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramSignal Descriptions Industry Standards Compliance StatementClock Control Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define EmacdscflagjabberBuffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module No Match Nomatch FlagInternal Memory Bus ArbiterMdio Module Interrupt ControlMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic Transmit DMA EngineTransmit Fifo MAC TransmitterMedia Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address MatchingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentReceive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Emac Control Module Interrupt Control Register Ewctl Emac Control Module RegistersAcronym Register Description Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsUserint Linkint Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP