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Peripheral Architecture
2.6.3Interrupt Control
The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to control the interrupt signal to the CPU:
∙The INTEN bit in the EMAC control module interrupt control register (EWCTL) globally enables and disables the interrupt signal to the CPU. The INTEN bit is used to drive the interrupt line low during interrupt processing so that upon reenabling the bit, the interrupt signal will rise if another interrupt condition exists; thus, creating a rising edge detectable by the CPU.
∙The EMAC control module interrupt timer count register (EWINTTCNT) is programmed with a value (EWINTTCNT) that counts down once EMAC/MDIO interrupts are enabled using EWCTL. The CPU interrupt signal is prevented from rising again until this count reaches 0.
EWINTTCNT has no effect on interrupts once the count reaches 0, so there is no induced interrupt latency on random sporadic interrupts. However, the count delays the issuance of a second interrupt immediately after a first. This protects the system from getting into an interrupt thrashing mode where the software interrupt service routine (ISR) completes processing just in time to get another interrupt. By postponing subsequent interrupts in a
EWINTTCNT reset value can be adjusted from within the ISR according to current system load, or simply set to a fixed value that assures a maximum number of interrupts per second.
The counter counts at the peripheral clock frequency of PLL1/6; its default reset count is 0 (inactive), its maximum value is 1 FFFFh (131 071).
2.7MDIO Module
The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC). The DM643x device supports a single PHY being connected to the EMAC at any given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU.
The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device without continuously performing MDIO module accesses. However, when the CPU must access the MDIO module for configuration and negotiation, the MDIO module performs the MDIO read or write operation independent of the CPU. This independent operation allows the processor to poll for completion or interrupt the CPU once the operation has completed.
2.7.1MDIO Module Components
The MDIO module (Figure 9) interfaces to the PHY components through two MDIO pins (MDCLK and MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module consists of the following logical components:
∙MDIO clock generator
∙Global PHY detection and link state monitoring
∙Active PHY monitoring
∙PHY register user access
28 Ethernet Media Access Controller (EMAC)/SPRU941A
Management Data Input/Output (MDIO) | Submit Documentation Feedback |
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