A-6
Cisco MGX 8800/8900 Series Hardware Installation Guide
Releases 2 - 5.2, Part Number OL-4545-01, Rev. H0, May 2006
Appendix
PXM45 Specifications
Processor clock speed and memory
specifics
Clock speed: 350 MHz internal, 100 MHz external
Flash memory: 2 MB
DRAM: 256 MB
•PXM45, introduced October 2000, with MGX
Release 2 software and 128 MB RAM
•PXM45/B, introduced October 2001, with MGX
Release 2.1 software and 256 MB RAM
•PXM45/C, introduced April 2003, with MGX
Release 4.0 software and 512 MB RAM.
Tertiary cache: 2 MB
Secondary cache: 256 KB
BRAM: 512 KB
Hard disk: 6 GB
Maximum switch fabric throughput 45 Gbps
Control access
Note These ports exist on the user
interface back cards.
•Control port: RJ-45 receptacle, EIA/TIA-232, DTE
mode, asynchronous interface, 19,200 baud, 1 start
bit, 1 stop bit, no parity bits
•Maintenance port: RJ-45 receptacle, EIA/TIA-232,
DTE mode, asynchronous interface, 19,200 baud, 1
start bit, 1 stop bit, no parity bits
•LAN port: RJ-45 receptacle, 10BASE-T,
802.3 Ethernet
Controller access port
Note This port exists on the PXM-HD
back card.
Connector: OC-3 SC
Alarm indicators (audible and visual) Central office-compatible alarm indicators and controls
through a DB-15 receptacle
BITS clock interface T1 and E1 with an RJ-48 receptacle
Synchronization
Note These clock sources satisfy
Stratum 3 requirements
8-kHz clock derived from the following sources:
•Internal 8-kHz clock (± 4.6 ppm)
•Recovered clock from service modules or trunk line
interfaces
•External BITS clock port
Power –48 VDC
Maximum power consumption See Table 3 -6
TableA-4 PXM45 Specifications (continued)
Specification Description