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Inter
INTEl Corporation
Table of Contents
Page
Introduction
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Chapter Part 1 Introduction to Functions of a Computer
Program Counter Jumps, Subroutines and the Stack
Instruction Register and Decoder
Control Circuitry
Address Registers
Arithmetic/Logic Unit ALU
Timing
Instruction Fetch
Memory Read
Memory Write
Wait memory synchronization
Module
MCS·SS Microcomputer System
Evolution
Introduction to MCS-85
Software Compatibility
MCS·S5 Special Peripheral Components
8155 =CE, 8156 =CE
·1. MCS·SS Basic System
Programmable Peripherals
Interfacing to MCS·80/8S Programmable Peripheral Components
MEMil. lOR
Interfacing to Standard Memory
Demultiplexing the BUS
Instruction CYCLE/ACCESS Time
System Performance
Distributed Processing
Conclusions THROUGHPUT/COST
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Functional Description
Page
·1 808SA CPU Functional Block Diagram
Whatsin the 808SA
Hexidecimal Binary AEH
Hexadecimalbinary A7H
122H
·38085A Hardware and SOFT· Ware RST Branch Locations
·28085A Clock Logic
·4INTERRUPT Masks SET Using SIM Instruction
·5RIM Read Interrupt Mask
When Inter· Rupt occurs
Name Priority
Type
Branched to
HOW the MCS·85SYSTEM Works
·8BASIC CPU Functions
·9 CPU Timing for Store Accumulator Direct STA Instruction
Functional Description
·12808SA Machine State Chart
·13OPCODE Fetch Machine Cycle of DCX Instruction
Lililili
Jl..Jl..Jl..J LIl..Jl..J ~
Memory Write MW
U- U-U
V V U
Lr \F LrLrU-U-U-U- U
\J li\ Lr V V- U V u u u U
~--r
·21 Hold VS Interrupt NON Halt
Resets Sets
RST 5.5 Mask
RST 6~5 Mask
RST 7.5 Mask
7J==- 10ms.c
= ~
Signals Function
ALE
AS-AI5 101M =x---C
Conclusion
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System Operating
Page
Mvim
LOA
STA
Lhld
System Operation
Address Assignment
To , , I X X X
·-·-1
Memory·Mapped
Interfacing to Standard BUS Memories
Interfacing to MCS·80 Peripherals
Dynamic RAM Interface
·3 MCS·80 Peripherals with 110 Mapped
Minimum MCS-85 System
Parts Functions
T1t
System Operation
Scale =11
·8 Expanded System
System Operation Expanded MCS·85 System
Parts Function
ROM/EPROM
CPU
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Functional Description
Page
Chapter 8080 Central Processor Unit
Registers
Instruction Register and Control
Arithmetic and Logic Unit ALU
Data Bus Buffer
Machine Cycle Identification
State Transition Sequence
Status Bit Definitions
$ no
Irr\
RL- rL- rL.-h rL-h -h rL-rL- r-L
State Associated Activities
LnLn
IrL
Hold Sequences
~ ~ ~~ w---t. ~~u----t
Wl ~ ~
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Page
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Page
Iiii
Condition
Instruction Set
Page
H,L
H,SP
000 B
011 E 100 H
Label
Instruction and Data Formats
Data Word
\JNN
Addressing Modes
Condition Flags
O o 1 1 o
Instruction SET Encyclopedia
Instruction SET
ADD M
Xchg
P,CY,AC
~-1 ~-·
R CY
«H L
P,AC
8085, 5
\ r
DAA
00 0 S S S
Cleared
Address,jng
ORA M
RLC
CMC
CMA
1 1 1 1
Condition
Cycles 2/5 8085,315 States 9/18 8085, 11/17
«SP
Flag Word
Pchl
Pop
16 8085, 18
1 0
NOP
RIM
SIM
8085A 8080Al8085A Instruction SET Index
Sossa
808SA
808SA Instruction SET Summary Contd
Device Specifications
Page
Inter
Inter
Absolute Maximum RATINGS·
LC~
Wait
Inter 8080Al8080A·1/8080A·2 Waveforms
Data and Instruction Formats
Inter8080Al8080A·118080A·2
Instruction Set Summary
Inter8080A/8080A·1/8080A·2
AH CPU Functional Block Diagram Configuration
8085AH Pin
8085AH/8085AH-2/8085AH-1
Interrupt Priority, Restart Address, and Sensitivity
Pin Description
Vee
Interrupt and Serial 1/0
Driving the X1 and X2 Inputs
Quartz Crystal Clock Driver
MHz Input Frequency External Clock
Driver Circuit
LC Tuned Circuit Clock Driver
RiD~
001
AH Machine State Chart
AH Basic System Timing
SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS·
8085AH/8085AH-2/8085AH-1 Characteristics
Bus Timing Specification as a Teye Dependent Symbol
8085AH 8085AH-2 8085AH-1
TlDW
8085AH/8085AH-2/8085AH-1 Waveforms
IntJ 8085AH/8085AH-2/8085AH-1
I8085AH/8085AH-2/8085AH-1
CPU Functional Block Diagram
SA Pin
Absolute Maximum Ratings
= ov ±5%, Vss = OV unless otherwise specified
TCYC ClK Cycle Period 320 2000
ClK low Time Standard ClK loading
120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising
Xi Rising to ClK Falling 150
Symbol Parameter 8085A2 8085A·22 Units Min Max
Ready Setup Time to leading Edge
Trailing Edge of Read to Re·Enabling
Address TRD Read or Inta to Valid Data
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Appendix
Page
Appendix AP.PLICATIONS of MCS-85
MCS-85 Applications
Baud Rates
111J
RLm
R14
LlL
PAt8~~P
Additional 808SA Interrupts
16K 32K
64K
Memory Addressing
As an example letslook at IntelsROM/EPROM family Fig
Ihl
YT~~
Static Memories
EJ EJ EJ
Data
DMA Direct Memory Access
Refresh
During initialization
D5H
A4H
LXI Sp
=11
System Timings
OT~
·2Clock Related Timing Vs MHz Considerations
2T-80
Memory Device Compatibility
Minimum System
AddreS? access TAD MEM Chip select access
Address access TAD MEM Chip select access
Output enable TRD MEM
BOSSA, A-2Memory Compatibility
Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE
Bus Compatibility Analysis see Figure
TDHR 160 ns
Bus Compatibility Analysis see Contd
Gates Flip Flops 15 ns 8216s 30 ns Flip flop
41 ns
200
Input Current TIL single load 40p,A 6mA Schottky or Htil
10p,A
TIL + 36 MOS
Schotiky or 1 Htil
Application Example
1 D1
333
Software
Temperature Sensor Flow Diagram
Thermistor Resistance Mapping
~.,.-~
Has the entire
JNZ search
Return
Clear HL
CRT Interface
RS·232C Interface Schematic
Output Routine
Fi1
POP !?
PP-l
HALFPrT
HOi
+ 6 =
HO =
Bf?E
01H
Cassette Recorder Interface
One Chip Magnetic Tape Interface Schematic
But
BLl2
T01 ~1V! A..OCeH
FeNO
JC TIl
Bf1
Additional Comments
A1·43
Temperature Sensor Code
Temperature Sensor Code Contd
Temperature Sensor Code Contd
Temperature Sensor Code Contd
CRT and Cassette Code
?Ece
E81B
BRm
Ep! l
08,.1
\/1
ES77 C2760S 102
ES7A Le?
E87B C2760S 104
06e9
SEce
3E01
0911 C2OC99 9914 C9
RERn Eight Opta ens
TI2
TIl . Repeat Until Full BrTE ASSEt-18LEr
BlnIN a ,38 Eurcd a
Tu30B
€18F2
089E
ErTIN
BITSr
Btl
RRcr
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Workshops
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Intel Workshops
Experience
Boston Area
Chicago Area
Dallas Area
SAN Francisco BAY Area
Introduction to Microprocessors
Lab sessions on SDK-8S System Design Kit
MCS-80/85 Microprocessors
Domestic Sales Offices
IntJ
~9Jf69rt,~~9
\.,1
Inter
Service Offices