Page
 Inter
 INTEl Corporation
 Table of Contents
Page
 Introduction
Page
 Chapter Part 1 Introduction to Functions of a Computer
 Program Counter Jumps, Subroutines and the Stack
Instruction Register and Decoder
 Arithmetic/Logic Unit ALU
Control Circuitry
Address Registers
Timing
 Memory Write
Instruction Fetch
Memory Read
Wait memory synchronization
 Module
 MCS·SS Microcomputer System
Evolution
 Introduction to MCS-85
 Software Compatibility
 MCS·S5 Special Peripheral Components
8155 =CE, 8156 =CE
 ·1. MCS·SS Basic System
 Interfacing to MCS·80/8S Programmable Peripheral Components
Programmable Peripherals
MEMil. lOR
 Interfacing to Standard Memory
Demultiplexing the BUS
 Distributed Processing
Instruction CYCLE/ACCESS Time
System Performance
Conclusions THROUGHPUT/COST
Page
 Functional Description
Page
 ·1 808SA CPU Functional Block Diagram
Whatsin the 808SA
 Hexadecimalbinary A7H
Hexidecimal Binary AEH
122H
 ·38085A Hardware and SOFT· Ware RST Branch Locations
·28085A Clock Logic
 ·4INTERRUPT Masks SET Using SIM Instruction
·5RIM Read Interrupt Mask
 Type
When Inter· Rupt occurs
Name Priority
Branched to
 HOW the MCS·85SYSTEM Works
·8BASIC CPU Functions
 ·9 CPU Timing for Store Accumulator Direct STA Instruction
 Functional Description
 ·12808SA Machine State Chart
 ·13OPCODE Fetch Machine Cycle of DCX Instruction
 Lililili
 Jl..Jl..Jl..J LIl..Jl..J ~
Memory Write MW
 U- U-U
 V V U
 Lr \F LrLrU-U-U-U- U
 \J li\ Lr V V- U V u u u U
~--r
 ·21 Hold VS Interrupt NON Halt
 RST 6~5 Mask
Resets Sets
RST 5.5 Mask
RST 7.5 Mask
 7J==- 10ms.c
 = ~
 Signals Function
ALE
 AS-AI5 101M =x---C
 Conclusion
Page
 System Operating
Page
 STA
Mvim
LOA
Lhld
 System Operation
Address Assignment
 To , , I X X X
 ·-·-1
Memory·Mapped
 Interfacing to MCS·80 Peripherals
Interfacing to Standard BUS Memories
Dynamic RAM Interface
 ·3 MCS·80 Peripherals with 110 Mapped
 Minimum MCS-85 System
Parts Functions
 T1t
 System Operation
Scale =11
 ·8 Expanded System
 ROM/EPROM
System Operation Expanded MCS·85 System
Parts Function
CPU
Page
 Functional Description
Page
 Chapter 8080 Central Processor Unit
 Registers
 Arithmetic and Logic Unit ALU
Instruction Register and Control
Data Bus Buffer
 Machine Cycle Identification
 State Transition Sequence
 Status Bit Definitions
 $ no
 Irr\
 RL- rL- rL.-h rL-h -h rL-rL- r-L
 State Associated Activities
 LnLn
 IrL
 Hold Sequences
 ~ ~ ~~ w---t. ~~u----t
 Wl ~ ~
Page
Page
Page
Page
 Iiii
Condition
 Instruction Set
Page
 000 B
H,L
H,SP
011 E 100 H
 Data Word
Label
Instruction and Data Formats
\JNN
 Addressing Modes
Condition Flags
 O o 1 1 o
Instruction SET Encyclopedia
 Instruction SET
 Xchg
ADD M
P,CY,AC
 ~-1 ~-·
R CY
 P,AC
«H L
8085, 5
 DAA
\ r
00 0 S S S
 Cleared
Address,jng
 ORA M
RLC
 CMA
CMC
1 1 1 1
 Condition
 Cycles 2/5 8085,315 States 9/18 8085, 11/17
«SP
 Pchl
Flag Word
Pop
 16 8085, 18
1 0
 NOP
RIM
 SIM
 8085A 8080Al8085A Instruction SET Index
 Sossa
 808SA
 808SA Instruction SET Summary Contd
 Device Specifications
Page
 Inter
 Inter
 Absolute Maximum RATINGS·
 LC~
 Wait
 Inter 8080Al8080A·1/8080A·2 Waveforms
 Data and Instruction Formats
 Inter8080Al8080A·118080A·2
Instruction Set Summary
 Inter8080A/8080A·1/8080A·2
 AH CPU Functional Block Diagram Configuration
8085AH Pin
 8085AH/8085AH-2/8085AH-1
 Pin Description
Interrupt Priority, Restart Address, and Sensitivity
Vee
 Interrupt and Serial 1/0
 Driving the X1 and X2 Inputs
 Driver Circuit
Quartz Crystal Clock Driver
MHz Input Frequency External Clock
LC Tuned Circuit Clock Driver
 RiD~
 001
 AH Machine State Chart
AH Basic System Timing
 SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS·
 8085AH/8085AH-2/8085AH-1 Characteristics
 Bus Timing Specification as a Teye Dependent Symbol
8085AH 8085AH-2 8085AH-1
 TlDW
 8085AH/8085AH-2/8085AH-1 Waveforms
 IntJ 8085AH/8085AH-2/8085AH-1
 I8085AH/8085AH-2/8085AH-1
 CPU Functional Block Diagram
SA Pin
 Absolute Maximum Ratings
= ov ±5%, Vss = OV unless otherwise specified
 120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising
TCYC ClK Cycle Period 320 2000
ClK low Time Standard ClK loading
Xi Rising to ClK Falling 150
 Trailing Edge of Read to Re·Enabling
Symbol Parameter 8085A2 8085A·22 Units Min Max
Ready Setup Time to leading Edge
Address TRD Read or Inta to Valid Data
Page
 Appendix
Page
 Appendix AP.PLICATIONS of MCS-85
 MCS-85 Applications
Baud Rates
 111J
 RLm
 R14
LlL
 PAt8~~P
 Additional 808SA Interrupts
 Memory Addressing
16K 32K
64K
As an example letslook at IntelsROM/EPROM family Fig
 Ihl
 YT~~
 Static Memories
 EJ EJ EJ
 DMA Direct Memory Access
Data
Refresh
 A4H
During initialization
D5H
LXI Sp
 =11
 System Timings
 OT~
 ·2Clock Related Timing Vs MHz Considerations
 2T-80
 Memory Device Compatibility
Minimum System
 Output enable TRD MEM
AddreS? access TAD MEM Chip select access
Address access TAD MEM Chip select access
BOSSA, A-2Memory Compatibility
 Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE
Bus Compatibility Analysis see Figure
 Gates Flip Flops 15 ns 8216s 30 ns Flip flop
TDHR 160 ns
Bus Compatibility Analysis see Contd
41 ns
 200
 TIL + 36 MOS
Input Current TIL single load 40p,A 6mA Schottky or Htil
10p,A
Schotiky or 1 Htil
 Application Example
 1 D1
333
 Software
 Temperature Sensor Flow Diagram
 Thermistor Resistance Mapping
~.,.-~
 Return
Has the entire
JNZ search
Clear HL
 CRT Interface
 RS·232C Interface Schematic
 Output Routine
Fi1
 PP-l
POP !?
HALFPrT
 + 6 =
HOi
HO =
 Bf?E
01H
 Cassette Recorder Interface
 One Chip Magnetic Tape Interface Schematic
 T01 ~1V! A..OCeH
But
BLl2
FeNO
 JC TIl
Bf1
 Additional Comments
 A1·43
 Temperature Sensor Code
 Temperature Sensor Code Contd
 Temperature Sensor Code Contd
 Temperature Sensor Code Contd
 CRT and Cassette Code
 BRm
?Ece
E81B
Ep! l
 08,.1
 ES7A Le?
\/1
ES77 C2760S 102
E87B C2760S 104
 SEce
06e9
3E01
 TI2
0911 C2OC99 9914 C9
RERn Eight Opta ens
TIl . Repeat Until Full BrTE ASSEt-18LEr
 €18F2
BlnIN a ,38 Eurcd a
Tu30B
089E
 Btl
ErTIN
BITSr
RRcr
Page
 Workshops
Page
 Intel Workshops
Experience
 Dallas Area
Boston Area
Chicago Area
SAN Francisco BAY Area
 Introduction to Microprocessors
Lab sessions on SDK-8S System Design Kit
 MCS-80/85 Microprocessors
 Domestic Sales Offices
 IntJ
 ~9Jf69rt,~~9
 \.,1
 Inter
 Service Offices