TH~INSTRUCTION SET

11

ANI da.fa

(A).... (A)'N;"fllM8;rll

The~ cc>mteht

" ..... secQnd byte of'the hi-

str4Jction is

. c.a~1y·ANOed with the con-

te~ts o:f·~he 'ace3mufator.'Theresult is pl~aee~ in'tr~;:acci.tm,u'atGt. the CV flag is c:le•• andAc,s .Ht(8oati}. The CV f'lagis

cleared andAC is.elto the OR'ingof bits 3 of the operaftds (8080).

1

XRA M (Exclusive OR Memory)

(A) - (A) -v- «H) (L))

The content of the memory location whose address is contained in the Hand L registers is exclusive-OR'dwith the con- teotof the accumulator. The result is P'tacedin the accumulator. The CY and AC

. '.......e cleared.

1

o

1

o

1

1

1

o

 

 

 

 

 

 

 

 

 

 

 

Cycles:

2

 

 

 

 

 

 

States:

7

 

 

 

 

 

Addressing:

reg. indirect

 

 

 

 

 

Flags:

Z,S,P,CY,AC

 

XRI data

 

(Exclusive OR immediate)

 

 

(A) -

(A).-v- (byte 2)

 

 

 

 

The content of the second byte of the in- struction is exclusive-OR'dwith the con- tent of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

1 1 1 o 1

1 o

 

 

data

 

 

 

 

Cycles:

2

 

States:

7

 

Addressing:

immediate

 

Flags:

Z,S,P,CY,AC

ORA r

(OR Register)

(A) -

(A) V (r)

 

The content of register r is inclusive-OR'd w.ith the content of the accumulator. The resuH is placed in the accumulator. The CY and AC flags are cleared.

Ii

I

 

1

o

1

1

o

S

S

S

 

 

 

 

 

 

 

 

 

Q-yGI$S:

1

 

 

Cycles:

1

 

 

 

Staltes:'

4

 

 

States:

4

 

 

 

Add:ress,jng:

register

Addressing:

register

 

 

Flags:

Z,S,P,CY,AC

 

 

Flags:

Z,S,P,CY,AC

 

• All mnemonics copyrighted © Intel Corporation 1976,

5-10

Page 95
Image 95
Intel MCS-80/85 manual Cleared, Address,jng

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.