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6-17

AFN-01835C

Page 126

Image 126

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.

Contents

Page Inter INTEl Corporation Table of Contents Page Introduction Page Chapter Part 1 Introduction to Functions of a Computer Program Counter Jumps, Subroutines and the Stack Instruction Register and Decoder Arithmetic/Logic Unit ALU Control CircuitryAddress Registers Timing Memory Write Instruction FetchMemory Read Wait memory synchronization Module MCS·SS Microcomputer System Evolution Introduction to MCS-85 Software Compatibility MCS·S5 Special Peripheral Components 8155 =CE, 8156 =CE ·1. MCS·SS Basic System Interfacing to MCS·80/8S Programmable Peripheral Components Programmable PeripheralsMEMil. lOR Interfacing to Standard Memory Demultiplexing the BUS Distributed Processing Instruction CYCLE/ACCESS TimeSystem Performance Conclusions THROUGHPUT/COSTPage Functional Description Page ·1 808SA CPU Functional Block Diagram Whatsin the 808SA Hexadecimalbinary A7H Hexidecimal Binary AEH122H ·38085A Hardware and SOFT· Ware RST Branch Locations ·28085A Clock Logic ·4INTERRUPT Masks SET Using SIM Instruction ·5RIM Read Interrupt Mask Type When Inter· Rupt occursName Priority Branched to HOW the MCS·85SYSTEM Works ·8BASIC CPU Functions ·9 CPU Timing for Store Accumulator Direct STA Instruction Functional Description ·12808SA Machine State Chart ·13OPCODE Fetch Machine Cycle of DCX Instruction Lililili Jl..Jl..Jl..J LIl..Jl..J ~ Memory Write MW U- U-U V V U Lr \F LrLrU-U-U-U- U \J li\ Lr V V- U V u u u U ~--r ·21 Hold VS Interrupt NON Halt RST 6~5 Mask Resets SetsRST 5.5 Mask RST 7.5 Mask 7J==- 10ms.c = ~ Signals Function ALE AS-AI5 101M =x---C Conclusion Page System Operating Page STA MvimLOA Lhld System Operation Address Assignment To , , I X X X ·-·-1 Memory·Mapped Interfacing to MCS·80 Peripherals Interfacing to Standard BUS MemoriesDynamic RAM Interface ·3 MCS·80 Peripherals with 110 Mapped Minimum MCS-85 System Parts Functions T1t System Operation Scale =11 ·8 Expanded System ROM/EPROM System Operation Expanded MCS·85 SystemParts Function CPUPage Functional Description Page Chapter 8080 Central Processor Unit Registers Arithmetic and Logic Unit ALU Instruction Register and ControlData Bus Buffer Machine Cycle Identification State Transition Sequence Status Bit Definitions $ no Irr\ RL- rL- rL.-h rL-h -h rL-rL- r-L State Associated Activities LnLn IrL Hold Sequences ~ ~ ~~ w---t. ~~u----t Wl ~ ~ Page Page Page Page Iiii Condition Instruction Set Page 000 B H,LH,SP 011 E 100 H Data Word LabelInstruction and Data Formats \JNN Addressing Modes Condition Flags O o 1 1 o Instruction SET Encyclopedia Instruction SET Xchg ADD MP,CY,AC ~-1 ~-· R CY P,AC «H L8085, 5 DAA \ r00 0 S S S Cleared Address,jng ORA M RLC CMA CMC1 1 1 1 Condition Cycles 2/5 8085,315 States 9/18 8085, 11/17 «SP Pchl Flag WordPop 16 8085, 18 1 0 NOP RIM SIM 8085A 8080Al8085A Instruction SET Index Sossa 808SA 808SA Instruction SET Summary Contd Device Specifications Page Inter Inter Absolute Maximum RATINGS· LC~ Wait Inter 8080Al8080A·1/8080A·2 Waveforms Data and Instruction Formats Inter8080Al8080A·118080A·2 Instruction Set Summary Inter8080A/8080A·1/8080A·2 AH CPU Functional Block Diagram Configuration 8085AH Pin 8085AH/8085AH-2/8085AH-1 Pin Description Interrupt Priority, Restart Address, and SensitivityVee Interrupt and Serial 1/0 Driving the X1 and X2 Inputs Driver Circuit Quartz Crystal Clock DriverMHz Input Frequency External Clock LC Tuned Circuit Clock Driver RiD~ 001 AH Machine State Chart AH Basic System Timing SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS· 8085AH/8085AH-2/8085AH-1 Characteristics Bus Timing Specification as a Teye Dependent Symbol 8085AH 8085AH-2 8085AH-1 TlDW 8085AH/8085AH-2/8085AH-1 Waveforms IntJ 8085AH/8085AH-2/8085AH-1 I8085AH/8085AH-2/8085AH-1 CPU Functional Block Diagram SA Pin Absolute Maximum Ratings = ov ±5%, Vss = OV unless otherwise specified 120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising TCYC ClK Cycle Period 320 2000ClK low Time Standard ClK loading Xi Rising to ClK Falling 150 Trailing Edge of Read to Re·Enabling Symbol Parameter 8085A2 8085A·22 Units Min MaxReady Setup Time to leading Edge Address TRD Read or Inta to Valid DataPage Appendix Page Appendix AP.PLICATIONS of MCS-85 MCS-85 Applications Baud Rates 111J RLm R14 LlL PAt8~~P Additional 808SA Interrupts Memory Addressing 16K 32K64K As an example letslook at IntelsROM/EPROM family Fig Ihl YT~~ Static Memories EJ EJ EJ DMA Direct Memory Access DataRefresh A4H During initializationD5H LXI Sp =11 System Timings OT~ ·2Clock Related Timing Vs MHz Considerations 2T-80 Memory Device Compatibility Minimum System Output enable TRD MEM AddreS? access TAD MEM Chip select accessAddress access TAD MEM Chip select access BOSSA, A-2Memory Compatibility Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE Bus Compatibility Analysis see Figure Gates Flip Flops 15 ns 8216s 30 ns Flip flop TDHR 160 nsBus Compatibility Analysis see Contd 41 ns 200 TIL + 36 MOS Input Current TIL single load 40p,A 6mA Schottky or Htil10p,A Schotiky or 1 Htil Application Example 1 D1 333 Software Temperature Sensor Flow Diagram Thermistor Resistance Mapping ~.,.-~ Return Has the entireJNZ search Clear HL CRT Interface RS·232C Interface Schematic Output Routine Fi1 PP-l POP !?HALFPrT + 6 = HOiHO = Bf?E 01H Cassette Recorder Interface One Chip Magnetic Tape Interface Schematic T01 ~1V! A..OCeH ButBLl2 FeNO JC TIl Bf1 Additional Comments A1·43 Temperature Sensor Code Temperature Sensor Code Contd Temperature Sensor Code Contd Temperature Sensor Code Contd CRT and Cassette Code BRm ?EceE81B Ep! l 08,.1 ES7A Le? \/1ES77 C2760S 102 E87B C2760S 104 SEce 06e93E01 TI2 0911 C2OC99 9914 C9RERn Eight Opta ens TIl . Repeat Until Full BrTE ASSEt-18LEr €18F2 BlnIN a ,38 Eurcd aTu30B 089E Btl ErTINBITSr RRcrPage Workshops Page Intel Workshops Experience Dallas Area Boston AreaChicago Area SAN Francisco BAY Area Introduction to Microprocessors Lab sessions on SDK-8S System Design Kit MCS-80/85 Microprocessors Domestic Sales Offices IntJ ~9Jf69rt,~~9 \.,1 Inter Service Offices

Intel MCS-80/85 manual 001

Models: MCS-80/85

8085AH/8085AH-2/8085AH-1

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Figure 8. MCS-85® Minimum System (Memory Mapped I/O)

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Figure 9. MCS-85® System (Using Standard Memories)

MCS-80/85 specifications