Intel MCS-80/85 manual Status Bit Definitions

Models: MCS-80/85

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Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status information on the data bus at the beginn ing of each machine cycle (during SYNC time). The following table defines the status information.

 

STATUS INFORMATION DEFINITION

 

Data Bus

 

Symbols

Bit

Definition

INTA*

DO

Acknowledge signal for INTE R R UPT re-

 

 

quest. Signal should be used to gate a re-

 

 

start instruction onto the data bus when

 

 

DBIN is active.

 

Dl

Indicates that the operation in the current

 

 

machine cycle will be a WR ITE memory

 

 

or OUTPUT function (WO = 0). Otherwise,

 

 

a READ memory or INPUT operation will

 

 

be executed.

STACK

D2

Indicates that the address bus holds the

 

 

pushdown stack address from the Stack

 

 

Pointer.

HLTA

D3

Acknowledge signal for HALT instruction.

OUT

D4

Indicates that the address bus contains the

 

 

address of an output device and the data

 

 

bus will contain the output data when

 

 

WR is active.

M,

D5

Provides a signal to indicate that the CPU

 

 

is in the fetch cycle for the first byte of

 

 

an instruction.

INP*

De

Indicates that the address bus contains the

 

 

address of an input device and the input

 

 

data should be placed on the data bus

 

 

when DBIN is active.

MEMR*

D7

Designates that the data bus will be used

 

 

for memory read data.

*These three status bits can be used to control the flow of data onto the 8080 data bus.

STATUS WORD CHART

/too 8080 STATUS LATCH

9

D,

D8

27

 

D3

3

 

 

D,

 

 

8080

4

 

D5

5

 

 

 

 

~!

 

 

 

6

 

SYNC ~

,DBIN r22-

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STATUS

 

22

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LATCH

 

 

 

 

 

 

 

 

 

 

 

5

'

 

Do t--

 

 

 

 

 

 

 

 

 

 

 

 

 

--4-

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~

 

 

 

 

 

 

~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

------g

 

 

 

 

 

 

Ta-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r,s-

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8212

 

 

'17""

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

:tt=

CLOCK GEN

 

I lTTLI

 

 

 

 

 

 

22

 

 

 

 

 

 

 

& DRIVER

 

 

 

 

 

 

 

 

 

 

 

 

 

~ g~; MO

OS,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13 12

'( 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~

SYNC

ST A TUS f ------ f . J' ----- 1

TYPE OF MACHINE CYCLE

INTA

WD

STACK HLTA OUT M1 INP MEMR

DBIN

 

 

 

 

 

 

 

 

 

 

 

 

Do

INTA

 

 

000000010

 

 

 

 

WO

1

1

0

1

0

1 0

1

1

 

 

STACK

000

1

100

0

0

o

 

HLTA

o

0

0

0

0

0

0

0

1

 

 

OUT

o

0

000

0

1

0

0

o

 

 

1

0

0

0

0

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

De

INP

o

0

000

1

000

o

 

MEMR

110100001

o

Table 4-1. 8080 Status Bit Definitions

4-6

Page 69
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Intel MCS-80/85 manual Status Bit Definitions

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.