inter8080Al8080A·118080A·2

Table 2. Instruction Set Summary

I~

!1

II

 

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

Instruction Code [1]

 

Operations

 

Cycles

 

 

Mnemonic

 

 

[ry 06 Os 04 03 02 01 DO

Description

 

[2]

 

 

MOVE, LOAD, AND STORE

 

 

 

 

 

 

 

 

MOVr1,r2

 

 

0 1 0 0 0 S S

S

Move register to register

 

5

 

 

MOVM,r.

 

 

0 1 1 1 0 S S

S

Move register to

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

memory

 

 

 

 

MOVr,M

 

 

0 1 0 0 0 1 1

0

Move memory to regis-

 

 

7

 

 

 

 

 

 

 

 

 

ter

 

 

 

 

MVlr

 

 

0 0 D 0 0 1 1

0

Move immediate regis-

 

 

 

 

 

 

 

 

 

 

 

 

ter

 

 

7

 

 

MVIM

 

 

0 0 1 1 0 1 1

0

Move immediate

 

 

10

 

 

 

 

 

 

 

 

 

memory

 

 

 

 

LXIB

 

 

0 0 0 0 0 0 0

1

Load immediate register

 

 

10

 

 

 

 

 

 

 

 

 

PairB & C

 

 

 

 

 

LXI 0

 

 

0 0 0 1 0 0 0

1

Load immediate register

 

 

10

 

 

 

 

 

 

 

 

 

PairO& E

 

 

 

 

 

LXI H

 

 

0 0 1 0 0 0 0

1

Load immediate register

 

 

10

 

 

 

 

 

 

 

 

 

PairH&L

 

 

 

 

 

STAXB

 

 

0 0 0 0 0 0 1

0

Store A indirect

 

 

7

 

 

STAXO

 

 

0 0 0 1 0 0 1

0

Store A indirect

 

 

7

 

 

LDAXB

 

 

0 0 0 0 1 0 1

0

Load A indirect

 

 

7

 

 

LOAXO

 

 

0 0 0 1 1 0 1

0

Load A indirect

 

 

7

 

 

STA

 

 

0 0 1 1 0 0 1

0

Store A direct

 

 

13

 

 

 

 

 

 

 

 

LOA

 

 

0 0 1 1 1 0 1

0

Load A direct

 

 

13

 

 

SHLO

 

 

0 0 1 0 0 0 1

0

Store H & L direct

 

 

16

 

 

LHLD

 

 

 

0 0 1 0 1 0 1

0

Load H & L direct

 

 

16

 

 

XCHG

 

 

1 1 1 0 1 0 1

1

Exchange 0 & E, H & L

 

 

4

 

 

 

 

 

 

 

 

 

Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STACKOPS

1 1 0 0 0 1 0

1

Push register Pair B &

 

 

11

 

 

PUSHB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C on stack

 

 

11

 

 

PUSH 0

 

 

1 1 0 1 0 1 0

1

Push register Pair 0 &

 

 

 

 

 

 

 

 

 

 

 

E on stack

 

 

11

 

 

PUSHH

 

1 1 1 0 0 1 0

1

Push register Pair H &

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L on stack

 

11

 

 

PUSH

 

 

 

1 1 1 1 0 1 0

1

Push A and Flags

 

 

 

 

PSW

 

 

 

 

 

 

on stack

 

 

 

 

 

POPB

 

1 1 0 0 0 0 0

1

Pop register Pair B &

 

10

 

 

 

 

 

 

 

 

 

C off stack

 

 

 

 

POP 0

 

1 1 0 1 0 0 0

1

Pop register Pair 0 &

 

10

 

 

 

 

 

 

 

 

 

 

 

E off stack

 

 

 

 

POPH

 

 

 

1 1 1 0 0 0 0

1

Pop register Pair H &

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Lofl stack

 

 

 

 

POPPSW

 

1 1 1 1 0 0 0

1

Pop A and Flags

 

10

 

 

 

 

 

 

 

 

 

off stack

 

 

 

 

 

XTHL

 

 

 

1 1 1 0 0 0 1

1

Exchange top of

 

 

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

stack, H & L

 

 

 

 

 

SPHL

 

1 1 1 1 1 0 0

1

H & L to stack pointer

 

5

 

 

LXI SP

 

0 0 1 1 0 0 0

1

Load immediate stack

 

10

 

 

 

 

 

 

 

 

 

pointer

 

 

 

 

INXSP

 

0.0 1 1 0 0 1

1

Increment stack pointer

 

5

 

 

OCXSP

 

0 0 1 1 1 0 1

1

Decrement stack

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

pointer

 

 

 

 

JUMP

 

 

 

 

 

 

 

 

 

 

 

 

 

JMP

 

1 1 0 0 0 0 1

1

Jump unconditional

 

10

 

 

JC

 

1 1 0 1 1 0 1

0

Jump on carry

 

10

 

 

JNC

 

1 1 0 1 0 0 1

0

Jump on no carry

 

10

 

 

JZ

 

1 1 0 0 1 0 1

0

Jump on zero

 

10

 

 

JNZ

 

1 1 0 0 0 0 1

0

Jump on no zero

 

10

 

 

JP

 

1 1 1 1 0 0 1

0

Jump on positive

 

10

 

 

JM

 

1 1 1 1 1 0 1

0

Jump on minus

 

10

 

 

JPE

 

1 1 1 0 1 0 1

0

Jump on parity even

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

Instruction Code [1]

 

Operations

 

Cycles

 

Mnemonic

[ry 06 Os 04 03 02 01 DO

Description

 

[2]

 

 

 

 

 

 

 

 

 

 

 

 

JPO

1 1 1 0 0 0 1

0

Jump on parity odd

 

10

 

PCHL

1 1 1 0 1 0 0

1

H & L to program

 

5

 

 

 

 

 

 

 

 

counter

 

 

 

CALL

1

 

1

0 0 1 1

0

1

Cali unconditional

 

17

 

CALL

 

 

 

CC

1

 

1

0 1 1 1

0

0

Cali on carry

 

11/17

 

CNC

1

 

1

0 1 0 1

0

0

Cali on no carry

 

11/17

 

CZ

1

 

1

0 0 1 1

0

0

Cali on zero

 

11/17

 

CNZ

1

 

1

0 0 0 1

0

0

Cali on no zero

 

11/17

 

CP

1

 

1

1 1 0 1

0

0

Cali on positive

 

11/17

 

CM

1

 

1

1 1 1 1

0

0

Cali on minus

 

11/17

 

CPE

1

 

1

1 0 1 1

0

O.

Cali on parity even

 

11/17

 

CPO

1

 

1

1 0 0 1

0

0

Cali on parity odd

 

11/17

 

RETURN

 

 

 

 

 

 

 

 

 

 

 

RET

1

 

1

0 0 1 0

0

1

Return

 

10

 

RC

1

 

1

0 1 1 0

0

0

Return on carry

 

5/11

 

RNC

1

 

1

0 1 0 0

0

0

Retu rn on no carry

 

5/11

 

RZ

1

 

1

0 0 1 0 0

0

Return on zero

 

5/11

 

RNZ

1

 

1

0 0 0 0

0

0

Return on no zero

 

5/11

 

RP

1

 

1

1 1 0 0

0

0

Return on positive

 

5/11

 

RM

1

 

1

1 1 1 0

0

0

Return on minus

 

5/11

 

RPE

1

 

1 1 0 1 0 0

0

Return on parity even

 

5/11

 

RPO

1 1 1 0 0 0 0

0

Return on parity odd

 

5/11

 

RESTART

 

 

 

 

 

 

 

 

 

11

 

RST

1 1 A A A 1 1

1

Restart

 

 

INCREMENT

AND DECREMENT

 

 

 

 

 

 

INRr

0

 

0 D D D 1 0

0

Increment register

 

5

 

DCRr

0 0

D D D 1 0

1

Decrement register

 

5

 

INRM

0 0

1 1 0 1 0

0

Increment memory

 

10

 

DCRM

0 0 1 1 0 1 0

1

Decrement memory

10

 

INXB

0 0 0 0 0 0 1

1

Increment B & C

5

 

 

 

 

 

 

 

 

registers

 

 

INXD

0

 

0

0 1 0 0 1

1

Increment D & E

5

 

 

 

 

 

 

 

 

registers

 

 

INXH

0 0 1 0 0 0 1

1

Increment H & L

5

 

 

 

 

 

 

 

 

registers

 

 

OCXB

0 0 0 0 1 0 1

1

Decrement B & C

5

 

OCXO

0 0 0 1 1 0 1

1

Decrement 0 & E

5

 

OCXH

0 0 1 0 1 0 1

1

Decrement H & L

 

5

 

ADD

1 0 0 0 0 S S

S

Add register to A

 

 

4

 

 

 

AOOr

 

 

 

AOCr

1 0 0 0 1 S S

S

Add register to A

 

 

4

 

 

 

 

 

 

 

 

with carry

 

 

 

 

AOOM

1 0 0 0 0 1 1

0

Add memory to A

 

 

7

 

AOCM

1 0 0 0 1 1 1

0

Add memory to A

 

 

7

 

 

 

 

 

 

 

 

with carry

 

 

7

 

AOI

1 1 0 0 0 1 1

0

Add immediate to A

 

 

 

ACI

1 1 0 0 1 1 1

0

Add immediate to A

 

 

7

 

 

 

 

 

 

 

 

with carry

 

 

 

 

DADB

0 0 0 0 1 0 0

1

Add B & C to H & L

 

 

10

 

DADO

0 0 0 1 1 0 0

1

Add 0 & E to H & L

 

 

10

 

OAOH

0 0 1 0 1 0 0

1

Add H & Lto H & L

 

 

10

 

DAOSP

0 0 1 1 1 0 0

1

Add stack pointer to

 

 

10

 

 

 

 

 

 

 

 

H&L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

II

I

'I

I

I ..

6-8

AFN-00735C

Page 117
Image 117
Intel MCS-80/85 manual Inter8080Al8080A·118080A·2, Instruction Set Summary

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.