Inter8080Al8080A·118080A·2 | Intel MCS-80/85 specification

inter8080Al8080A·118080A·2

Table 2. Instruction Set Summary

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												Clock
					Instruction Code [1]			Operations				Cycles
	Mnemonic				[ry 06 Os 04 03 02 01 DO			Description				[2]
	MOVE, LOAD, AND STORE
	MOVr1,r2				0 1 0 0 0 S S		S	Move register to register				5
	MOVM,r.				0 1 1 1 0 S S		S	Move register to				7
	MOVM,r.				0 1 1 1 0 S S		S	Move register to
								memory
	MOVr,M				0 1 0 0 0 1 1		0	Move memory to regis-				7
								ter				7
	MVlr				0 0 D 0 0 1 1		0	Move immediate regis-
								ter				7
	MVIM				0 0 1 1 0 1 1		0	Move immediate				10
								memory				10
	LXIB				0 0 0 0 0 0 0		1	Load immediate register				10
								PairB & C
	LXI 0				0 0 0 1 0 0 0		1	Load immediate register				10
								PairO& E
	LXI H				0 0 1 0 0 0 0		1	Load immediate register				10
								PairH&L
	STAXB				0 0 0 0 0 0 1		0	Store A indirect				7
	STAXO				0 0 0 1 0 0 1		0	Store A indirect				7
	LDAXB				0 0 0 0 1 0 1		0	Load A indirect				7
	LOAXO				0 0 0 1 1 0 1		0	Load A indirect				7
	STA				0 0 1 1 0 0 1		0	Store A direct				13
	STA				0 0 1 1 0 0 1		0	Store A direct				13
	LOA				0 0 1 1 1 0 1		0	Load A direct				13
	SHLO				0 0 1 0 0 0 1		0	Store H & L direct				16
	LHLD				0 0 1 0 1 0 1		0	Load H & L direct				16
	XCHG				1 1 1 0 1 0 1		1	Exchange 0 & E, H & L				4
								Registers
								Registers
	STACKOPS				1 1 0 0 0 1 0		1	Push register Pair B &				11
	PUSHB
	PUSHB
								C on stack				11
	PUSH 0				1 1 0 1 0 1 0		1	Push register Pair 0 &				11
								E on stack				11
	PUSHH				1 1 1 0 0 1 0		1	Push register Pair H &
	PUSHH				1 1 1 0 0 1 0		1	Push register Pair H &
								L on stack				11
	PUSH				1 1 1 1 0 1 0		1	Push A and Flags				11
	PSW							on stack
	POPB				1 1 0 0 0 0 0		1	Pop register Pair B &				10
								C off stack
	POP 0				1 1 0 1 0 0 0		1	Pop register Pair 0 &				10
	POP 0				1 1 0 1 0 0 0		1	Pop register Pair 0 &				10
								E off stack
	POPH				1 1 1 0 0 0 0		1	Pop register Pair H &				10
	POPH				1 1 1 0 0 0 0		1	Pop register Pair H &				10
								Lofl stack
	POPPSW				1 1 1 1 0 0 0		1	Pop A and Flags				10
								off stack
	XTHL				1 1 1 0 0 0 1		1	Exchange top of				18
	XTHL				1 1 1 0 0 0 1		1	Exchange top of				18
								stack, H & L
	SPHL				1 1 1 1 1 0 0		1	H & L to stack pointer				5
	LXI SP				0 0 1 1 0 0 0		1	Load immediate stack				10
								pointer
	INXSP				0.0 1 1 0 0 1		1	Increment stack pointer				5
	OCXSP				0 0 1 1 1 0 1		1	Decrement stack				5
	OCXSP				0 0 1 1 1 0 1		1	Decrement stack				5
								pointer
	JUMP
	JMP				1 1 0 0 0 0 1		1	Jump unconditional				10
	JC				1 1 0 1 1 0 1		0	Jump on carry				10
	JNC				1 1 0 1 0 0 1		0	Jump on no carry				10
	JZ				1 1 0 0 1 0 1		0	Jump on zero				10
	JNZ				1 1 0 0 0 0 1		0	Jump on no zero				10
	JP				1 1 1 1 0 0 1		0	Jump on positive				10
	JM				1 1 1 1 1 0 1		0	Jump on minus				10
	JPE				1 1 1 0 1 0 1		0	Jump on parity even				10

												Clock
					Instruction Code [1]				Operations			Cycles
		Mnemonic	[ry 06 Os 04 03 02 01 DO						Description			[2]

		JPO	1 1 1 0 0 0 1					0	Jump on parity odd			10
		PCHL	1 1 1 0 1 0 0					1	H & L to program			5
									counter
		CALL	1		1	0 0 1 1	0	1	Cali unconditional			17
		CALL	1		1	0 0 1 1	0	1	Cali unconditional			17
		CC	1		1	0 1 1 1	0	0	Cali on carry			11/17
		CNC	1		1	0 1 0 1	0	0	Cali on no carry			11/17
		CZ	1		1	0 0 1 1	0	0	Cali on zero			11/17
		CNZ	1		1	0 0 0 1	0	0	Cali on no zero			11/17
		CP	1		1	1 1 0 1	0	0	Cali on positive			11/17
		CM	1		1	1 1 1 1	0	0	Cali on minus			11/17
		CPE	1		1	1 0 1 1	0	O.	Cali on parity even			11/17
		CPO	1		1	1 0 0 1	0	0	Cali on parity odd			11/17
		RETURN
		RET	1		1	0 0 1 0	0	1	Return			10
		RC	1		1	0 1 1 0	0	0	Return on carry			5/11
		RNC	1		1	0 1 0 0	0	0	Retu rn on no carry			5/11
		RZ	1		1	0 0 1 0 0		0	Return on zero			5/11
		RNZ	1		1	0 0 0 0	0	0	Return on no zero			5/11
		RNZ	1		1	0 0 0 0	0	0	Return on no zero			5/11
		RP	1		1	1 1 0 0	0	0	Return on positive			5/11
		RM	1		1	1 1 1 0	0	0	Return on minus			5/11
		RPE	1		1 1 0 1 0 0			0	Return on parity even			5/11
		RPO	1 1 1 0 0 0 0					0	Return on parity odd			5/11
		RESTART										11
		RST	1 1 A A A 1 1					1	Restart			11
		INCREMENT	AND DECREMENT
		INRr	0		0 D D D 1 0			0	Increment register			5
		DCRr	0 0			D D D 1 0		1	Decrement register			5
		INRM	0 0			1 1 0 1 0		0	Increment memory			10
		DCRM	0 0 1 1 0 1 0					1	Decrement memory			10
		INXB	0 0 0 0 0 0 1					1	Increment B & C			5
									registers
		INXD	0		0	0 1 0 0 1		1	Increment D & E			5
									registers
		INXH	0 0 1 0 0 0 1					1	Increment H & L			5
									registers
		OCXB	0 0 0 0 1 0 1					1	Decrement B & C			5
		OCXO	0 0 0 1 1 0 1					1	Decrement 0 & E			5
		OCXH	0 0 1 0 1 0 1					1	Decrement H & L			5
		ADD	1 0 0 0 0 S S					S	Add register to A			4
		ADD
		AOOr
		AOCr	1 0 0 0 1 S S					S	Add register to A			4
									with carry
		AOOM	1 0 0 0 0 1 1					0	Add memory to A			7
		AOOM	1 0 0 0 0 1 1					0	Add memory to A			7
		AOCM	1 0 0 0 1 1 1					0	Add memory to A			7
									with carry			7
		AOI	1 1 0 0 0 1 1					0	Add immediate to A			7
		ACI	1 1 0 0 1 1 1					0	Add immediate to A			7
									with carry
		DADB	0 0 0 0 1 0 0					1	Add B & C to H & L			10
		DADO	0 0 0 1 1 0 0					1	Add 0 & E to H & L			10
		OAOH	0 0 1 0 1 0 0					1	Add H & Lto H & L			10
		DAOSP	0 0 1 1 1 0 0					1	Add stack pointer to			10
									H&L

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Image 117

Intel MCS-80/85 manual Inter8080Al8080A·118080A·2, Instruction Set Summary

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.

Contents

Page Inter INTEl Corporation Table of Contents Page Introduction Page Chapter Part 1 Introduction to Functions of a Computer Instruction Register and Decoder Program Counter Jumps, Subroutines and the Stack Address Registers Control CircuitryArithmetic/Logic Unit ALU Timing Memory Read Instruction FetchMemory Write Wait memory synchronization Module Evolution MCS·SS Microcomputer System Introduction to MCS-85 Software Compatibility 8155 =CE, 8156 =CE MCS·S5 Special Peripheral Components ·1. MCS·SS Basic System Interfacing to MCS·80/8S Programmable Peripheral Components Programmable PeripheralsMEMil. lOR Demultiplexing the BUS Interfacing to Standard Memory System Performance Instruction CYCLE/ACCESS TimeDistributed Processing Conclusions THROUGHPUT/COSTPage Functional Description Page Whatsin the 808SA ·1 808SA CPU Functional Block Diagram Hexadecimalbinary A7H Hexidecimal Binary AEH122H ·28085A Clock Logic ·38085A Hardware and SOFT· Ware RST Branch Locations ·5RIM Read Interrupt Mask ·4INTERRUPT Masks SET Using SIM Instruction Name Priority When Inter· Rupt occursType Branched to ·8BASIC CPU Functions HOW the MCS·85SYSTEM Works ·9 CPU Timing for Store Accumulator Direct STA Instruction Functional Description ·12808SA Machine State Chart ·13OPCODE Fetch Machine Cycle of DCX Instruction Lililili Memory Write MW Jl..Jl..Jl..J LIl..Jl..J ~ U- U-U V V U Lr \F LrLrU-U-U-U- U ~--r \J li\ Lr V V- U V u u u U ·21 Hold VS Interrupt NON Halt RST 5.5 Mask Resets SetsRST 6~5 Mask RST 7.5 Mask 7J==- 10ms.c = ~ ALE Signals Function AS-AI5 101M =x---C Conclusion Page System Operating Page LOA MvimSTA Lhld Address Assignment System Operation To , , I X X X Memory·Mapped ·-·-1 Interfacing to MCS·80 Peripherals Interfacing to Standard BUS MemoriesDynamic RAM Interface ·3 MCS·80 Peripherals with 110 Mapped Parts Functions Minimum MCS-85 System T1t Scale =11 System Operation ·8 Expanded System Parts Function System Operation Expanded MCS·85 SystemROM/EPROM CPUPage Functional Description Page Chapter 8080 Central Processor Unit Registers Arithmetic and Logic Unit ALU Instruction Register and ControlData Bus Buffer Machine Cycle Identification State Transition Sequence Status Bit Definitions $ no Irr\ RL- rL- rL.-h rL-h -h rL-rL- r-L State Associated Activities LnLn IrL Hold Sequences ~ ~ ~~ w---t. ~~u----t Wl ~ ~ Page Page Page Page Condition Iiii Instruction Set Page H,SP H,L000 B 011 E 100 H Instruction and Data Formats LabelData Word \JNN Condition Flags Addressing Modes Instruction SET Encyclopedia O o 1 1 o Instruction SET Xchg ADD MP,CY,AC R CY ~-1 ~-· P,AC «H L8085, 5 DAA \ r00 0 S S S Address,jng Cleared RLC ORA M CMA CMC1 1 1 1 Condition «SP Cycles 2/5 8085,315 States 9/18 8085, 11/17 Pchl Flag WordPop 1 0 16 8085, 18 RIM NOP SIM 8085A 8080Al8085A Instruction SET Index Sossa 808SA 808SA Instruction SET Summary Contd Device Specifications Page Inter Inter Absolute Maximum RATINGS· LC~ Wait Inter 8080Al8080A·1/8080A·2 Waveforms Data and Instruction Formats Instruction Set Summary Inter8080Al8080A·118080A·2 Inter8080A/8080A·1/8080A·2 8085AH Pin AH CPU Functional Block Diagram Configuration 8085AH/8085AH-2/8085AH-1 Pin Description Interrupt Priority, Restart Address, and SensitivityVee Interrupt and Serial 1/0 Driving the X1 and X2 Inputs MHz Input Frequency External Clock Quartz Crystal Clock DriverDriver Circuit LC Tuned Circuit Clock Driver RiD~ 001 AH Basic System Timing AH Machine State Chart SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS· 8085AH/8085AH-2/8085AH-1 Characteristics 8085AH 8085AH-2 8085AH-1 Bus Timing Specification as a Teye Dependent Symbol TlDW 8085AH/8085AH-2/8085AH-1 Waveforms IntJ 8085AH/8085AH-2/8085AH-1 I8085AH/8085AH-2/8085AH-1 SA Pin CPU Functional Block Diagram = ov ±5%, Vss = OV unless otherwise specified Absolute Maximum Ratings ClK low Time Standard ClK loading TCYC ClK Cycle Period 320 2000120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising Xi Rising to ClK Falling 150 Ready Setup Time to leading Edge Symbol Parameter 8085A2 8085A·22 Units Min MaxTrailing Edge of Read to Re·Enabling Address TRD Read or Inta to Valid DataPage Appendix Page Appendix AP.PLICATIONS of MCS-85 Baud Rates MCS-85 Applications 111J RLm LlL R14 PAt8~~P Additional 808SA Interrupts 64K 16K 32KMemory Addressing As an example letslook at IntelsROM/EPROM family Fig Ihl YT~~ Static Memories EJ EJ EJ DMA Direct Memory Access DataRefresh D5H During initializationA4H LXI Sp =11 System Timings OT~ ·2Clock Related Timing Vs MHz Considerations 2T-80 Minimum System Memory Device Compatibility Address access TAD MEM Chip select access AddreS? access TAD MEM Chip select accessOutput enable TRD MEM BOSSA, A-2Memory Compatibility Bus Compatibility Analysis see Figure Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE Bus Compatibility Analysis see Contd TDHR 160 nsGates Flip Flops 15 ns 8216s 30 ns Flip flop 41 ns 200 10p,A Input Current TIL single load 40p,A 6mA Schottky or HtilTIL + 36 MOS Schotiky or 1 Htil Application Example 333 1 D1 Software Temperature Sensor Flow Diagram ~.,.-~ Thermistor Resistance Mapping JNZ search Has the entireReturn Clear HL CRT Interface RS·232C Interface Schematic Fi1 Output Routine PP-l POP !?HALFPrT + 6 = HOiHO = 01H Bf?E Cassette Recorder Interface One Chip Magnetic Tape Interface Schematic BLl2 ButT01 ~1V! A..OCeH FeNO Bf1 JC TIl Additional Comments A1·43 Temperature Sensor Code Temperature Sensor Code Contd Temperature Sensor Code Contd Temperature Sensor Code Contd CRT and Cassette Code E81B ?EceBRm Ep! l 08,.1 ES77 C2760S 102 \/1ES7A Le? E87B C2760S 104 SEce 06e93E01 RERn Eight Opta ens 0911 C2OC99 9914 C9TI2 TIl . Repeat Until Full BrTE ASSEt-18LEr Tu30B BlnIN a ,38 Eurcd a€18F2 089E BITSr ErTINBtl RRcrPage Workshops Page Experience Intel Workshops Chicago Area Boston AreaDallas Area SAN Francisco BAY Area Lab sessions on SDK-8S System Design Kit Introduction to Microprocessors MCS-80/85 Microprocessors Domestic Sales Offices IntJ ~9Jf69rt,~~9 \.,1 Inter Service Offices