For a typical calculation, see the example below.

EXAMPLE

To produce 2400 baud with the standard 6.144 MHz crystal:

2400

(6.144 X 106) + 2

 

83 + 14 (HO

14 (HO

(6.144 X 106 +2)

2400

- 83

 

(HO'

[(61442~O~06+ 2)_ 83J

 

+ 14 = 85.5

~ 86

(HO'

8610 = 0056H

(HO

0157H = BITTIME

To determine the true data rate this parameter will produce, substitute into equation (6):

6.144 X 106 + 2

Date Rate = 83 + 14(86)

=2387 baud, which is 0.54% slow.

For 9600 baud, the same calculations will yield (HO'

=17, which is actually 0.3% slow; a sizzling 19200 baud or 38400 baud could each be generated to with- in 5% if (HU' = 6 or O! Table 9 presents the param- eters for several standard baud rates.

Notice that the resolution of the delay algorithm - the difference between bit times resulting from parameters which differ by one - is 14 machine cycles. As a result, the true bit delay produced can always manage to be within ±2.3 fJsec of the delay

desired. This guarantees that at rates up to 9600 baud, where each bit time is at least 104 fJsec wide, some value of BITTIME can be found which will be accurate to within 2.2%.

BAUD RATE IDENTIFICATION ROUTINE

The function of BRID is to compute the appropri- ate parameters BITTIME and HALFBIT. It accom- plishes this by observing the data pattern received when the space bar is pressed on the console device. Since a space character has the ASCII code 20H = 001 OOOOOB, the pattern represented back in Figure 4 is transmitted. Notice that the initial Zero level is 6 bits wide. Suppose it could be determined that this corresponds to M machine cycles. Then one bit would correspond to (M+6) machine cycles. The reason for dividing down a space several bits long is so that any distortion caused by the signal rise and fall times, or any lack of pre- cision in detecting the two transitions, will be reduced by a factor of six. Since the bit period of COUT and CIN is 83 + 14 (HO',BRID must gener- ate a value (HOi such that:

M + 6 =

83 + 14 (HOi

(7)

(HOi

(M + 6) -

83

(8)

14

 

 

 

 

I

M

(approximately)

(9)

(HO =

84 - 6

This value can be determined by setting register pair HL to -6, then incrementing it once every 84 machine cycles during the period that the incom-

f

\:

I:,

1",1.,'.'

I

!

I

II

!,

I

Table 9

DELAY PARAMETERS FOR STANDARD BAND RATES USING 6.144 MHz CRYSTAL

TARGET

(HL)'10

(HL)' 16

(HL) or

 

 

 

 

ACTUAL

%

BAUD

BITTIME

HALFBIT

 

 

 

BAUD RATE

(See Text)

(See Text)

 

 

 

 

 

RATE

(See Text)

 

 

 

 

PRODUCED

 

ERROR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

110

1989

07C5

08C6

04E3

 

 

 

109.99

-0.006

 

 

150

1457

05Bl

06B2

0309

 

 

 

149.99

-0.005

300

726

0206

 

0307

026C

 

 

 

299.80

-0.068

600

360

0168

 

0269

01A5

 

 

 

599.65

-0.059

 

1200

177

OOBl

01B2

0159

 

 

 

1199.5

-0.039

2400

86

0056

 

0157

012C

 

 

2386.9

-0.547

4800

40

0028

 

0129

0115

 

 

4777.6

-0.469

 

 

 

 

~600

17

0011

 

0112

0109

 

 

 

9570.1

-0.312

19200

6

0006

 

0107

0104

 

 

18395.2

-4.37

 

 

 

 

 

 

 

 

 

 

 

 

A1-36

Page 177
Image 177
Intel MCS-80/85 manual + 6 =, HOi, Ho =

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.