I

I'

~~

I,"

POP H

POP !?

EI

RFT

INPUT ROUTINE

The console input routine uses the opposite pro- cedure; instead of moving a bit from register C to the CY, then to A7, then to SOD, CIN loads a bit from SID into A7, then moves it to CY, then into register C.

First, set up the CPU as before:

CHI PUSH H

PI

!,!\,1I B.:?

When a start bit transition arrives, the first sam- pling should not be taken until the middle of the first data bit, one and one-half bit times after the transition. Await the start bit transition, then set up the delay parameter for one-half bit time:

CIi'

RIl'l

 

(4)

 

')PA

A

<4>

 

m

(Ii

<7~.\

 

LHU'

HALFPrT

'-::1t:>

Loop for one-half bit time before starting to sample data:

CI2'

[:ofF.'

L

((i:.

 

mz

(12

([I)

 

DCP

H

.:[:..,

 

..TN:

CI2

,:.[:,':,

Wait until the middle of the next bit before sam- pling SID, then move the data bit into CY:

eB:

LHLf:t

BITTH1E

<16)

C14:

C(:P

L

;;c·)

 

.m:

Cf4

<O:i

 

[oCP-

H

<e')

 

.m:

(:14

W)

 

RIM

 

<4)

 

PP-l

 

<:4>

Decrement the bit counter. If this is the ninth cycle, the 8 data bits are in register C, so quit (the first stop bit will already have been received, and be in CY):

[)CP

P

<4)

..1:

CIS

(7)

Otherwise, continue. Rotate the data bit right into register C, and repeat the cycle:

~10Y

A,C

{4>

RAR

 

<.f>

NOli

C.F!

{,~)

NOP

CE

<4)

..Tt1P

<113::'

(A NOP is needed to make the COUT and CIN loops exactly equal in number of machine cycles, so that each can use the same delay parameter.) Restore status and return.

CI5 POP H

E1

FH

TIMING ANALYSIS

COUT and CIN now need to be provided with parameters for BITTIME and HALFBIT. It can be seen from the above code that each routine uses 61 + D machine cycles per input or output bit, where D is the number of cycles spent in either four line delay segmen t. If (H) and (L) are the contents of the Hand L registers going into this section of code, then:

D = 22+«U-I)X 14+«H)-l)X

 

 

 

[(255 X 14)+25]

(1)

If (H)' -

(H) - I, (U' == (U - I, and

 

 

 

(HU' == 256 (H)' + (U'

(2)

then

 

22 + 14 (U'+ 3595 (H)'

 

D

 

(3)

This can be approximated by:

 

D

=

22 + 14 (HU'

(4)

This approximation is exact for (H)' = 0; otherwise, it is accurate to within 0.3%. Thus each loop of COUT or CIN uses a total of:

C = 61 + D = 83 + 14 (HU' machine cycles (5)

Each machine cycle uses two crystal cycles in the 8085, so the resulting data rate is:

B = cycle frequency

C

(crystal frequency) +2

(6)

83 + 14 (HU'

 

A1-35

Page 176
Image 176
Intel MCS-80/85 manual PP-l, Pop !?, HALFPrT

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.