THE INSTRUCTION SET

Byte I

 

Three-Byte Instructions

I

 

I I I I

I I I 0

One . 0

7

 

O. Op Code

Byte 1 0

I

I

I

Two.L -7

Do--- I } orData

Byte l_7I

I_D---JOIAddress

Three

0

 

 

.

5.4ADDRESSING MODES:

Often the data that is to be operated on is stored in memory. When multi-byte numeric data is used, the data, like instructions, is stored in successive memory locations, with the least significant byte first, follow- ed by increasingly significant bytes. The 8085A has four different modes for addressing data stored in memory or in registers:

•Direct - Bytes 2 and 3 of the instruction contain the exact memory ad- dress of the data item (the low- order bits of the address are in byte 2, the high-order bits in byte 3).

•Register - The instruction specifies the register or register pair in which the data is located.

•Register Indirect - The instruction specifies a register pair which contains the memory address where the data is located (the high-order bits of the. address are in the first register of the pair the low-order bits in the second).

•Immediate - The instruction contains the data itself. This is either an 8-bit quantity or a 16-bit quanti- ty (least significant byte first, most significant byte second).

Unless directed by an interrupt or branch in- stitution, the execution of instructions pro- ceeds through consecutively increasing memory locations. A branch instruction can specify the address of the next instruction to be executed in one of two ways:

•Direct - The branch instruction contains the address of the next instruc- tion to be executed. (Except for the "RST' instruction, byte 2 contains the low-order address and byte 3 the high-order ad- dress.)

•Register Indirect - The branch instruc- tion indicates a register-pair which contains the address of the next instruction to be ex- ecuted. (The high-order bits of the address are in the first register of the pair, the low- order bits in the second.)

The RST instruction is a special one-byte call in- struction (usually used during interrupt se- quences). RST includes a three-bit field; pro- gram control is transferred to the instruction whose address is eight times the contents of this three-bit field.

5.5CONDITION FLAGS:

There are five condition flags associated with the execution of instructions on the 8085A. They are Zero, Sign, Parity, Carry, and Auxiliary Carry. Each is represented by a 1-bit register (or flip-flop) in the CPU. A flag is set by forCing the bit to 1; it is reset by forCing the bit to O.

Unless indicated otherwise, when an instruc- tion affects a flag, it affects it in the following manner:

Zero: If the result of an instruction has the value 0, this flag is set; otherwise it is reset.

Sign:

If the most significant bit of the

 

result of the operation has the

 

value 1, this flag is set; other-

 

wise it is reset.

Parity:

If the modulo 2 sum of the bits

 

of the result of the operation is

 

0, (Le., if the result has even

 

parity), this flag is set; other-

 

wise it is reset (Le., if the result

 

has odd parity).

Carry:

If the instruction resulted in a

 

carry (from addition), or a bor-

 

row (from subtraction or a com-

 

parison) out of the high-order

 

bit, this flag is set; otherwise it

 

is reset.

Auxiliary Carry: If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the aux- iliary carry is set; otherwise it is reset. This flag is affected by single-precision additions, sub- tractions, increments, decre- ments, comparisons, and logi- cal operations, but is principal- ly used with additions and in- crements preceding a DAA (Decimal Adjust Accumulator) instruction.

*AII mnemonics copyrighted©lntel Corporation 1976.

5-3

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Intel MCS-80/85 manual Addressing Modes, Condition Flags
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MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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