Lc~ | Intel MCS-80/85 specs

8080Al8080A·1/8080A·2

A.C. CHARACTERISTICS (8080A) (TA = O°C to 70°C, VOO = +12V ±5%, Vee = +5V ±5%, Vee = -5V ±5%, Vss =OV; unless otherwise noted)

											·1	·1	·2		·2
	Symbol				Parameter			Min.		Max.	Min.	Max.	Min.		Max.	Unit		Test Condition

	tCy(3)			Clock Period				0.48		2.0	0.32	2.0	0.38		2.0	"sec

	tr,tl			Clock Rise and Fall Time				0		50	0	25	0		50	nsec
	tr,tl			Clock Rise and Fall Time				0		50	0	25	0		50	nsec

	t01			01 Pulse Width				60			50		60			nsec

	t02			02 Pulse Width				220			145		175			nsec

	tD1			Delay 01 to 02				0			0		0			nsec

	tD2			Delay 02 to 01				70			60		70			nsec
	tD2			Delay 02 to 01				70			60		70			nsec

	tD3			Delay 01 to 02 Leading Edges				80			60		70			nsec

	tDA			Address Output Delay From 02						200		150			175	nsec	}CL=100 pF
	too			Data Output Delay From 02						220		180			200	nsec

	tDC			Signal Output Delay From 02 or 02 (SYNC, WR, WAIT, HLDA)						120		110			120	nsec	} CL=50pF
	tDC			Signal Output Delay From 02 or 02 (SYNC, WR, WAIT, HLDA)						120		110			120	nsec

	tDF			DBI N Delay From 02				25		140	25	130	25		140	nsec
	tDF			DBI N Delay From 02				25		140	25	130	25		140	nsec

	tOl[11			Delay for Input Bus to Enter Input Mode						tDF		tDF			tDF	nsec

	tDS1			Data Setup Time During 01 and DBIN				30			10		20			nsec
	tDS1			Data Setup Time During 01 and DBIN				30			10		20			nsec
	tDS2			Data Setup Time to 02 During DBIN				150			120		130			nsec
	tDH(1)			Data Holt time From 02 During DBIN				(1)			(1)		(1)			nsec

	tiE			INTE Output Delay From 02						200		200			200	nsec		CL=50 pF
	tiE			INTE Output Delay From 02						200		200			200	nsec		CL=50 pF
	tRS			READY Setup Time During 02				120			90		90			nsec
	tHS			HOLD Setup Time to 02				140			120		120			nsec

	tiS			INT Setup Time During 02				120			100		100			nsec

	tH			Hold Time From 02 (READY, INT, HOLD)				0			0		0			nsec

	tFO			Delay to Float During Hold (Address and Data Bus)						120		120			120	nsec	-
	tAW			Address Stable Prior to WR				(5)			(5)		(5)			nsec



	tow			Output Data Stable Prior to WR				(6)			(6)		(6)			nsec

	two			Output Data Stable From WR				(7)			(7)		(7)			nsec		CL = 100 pF: Address, Data
	two			Output Data Stable From WR				(7)			(7)		(7)			nsec

	tWA			Address Stable From WR				(7)			(7)		(7)			nsec
	tWA			Address Stable From WR				(7)			(7)		(7)			nsec		CL = 50 pF: WR,HLDA,DBIN
																		CL = 50 pF: WR,HLDA,DBIN

	tHF			HLDA to Float Delay				(8)			(8)		(8)			nsec
	tHF			HLDA to Float Delay				(8)			(8)		(8)			nsec
	tWF			WR to Float Delay				(9)			(9)		(9)			nsec
																	-
	tAH			Address Hold Time After DBIN During HLDA				-20			-20		- 20			nsec	-

A.C. TESTING LOAD CIRCUIT

DEVICE

UNDER

TEST

Cl~ 100pF

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Cl INCLUDES JIG CAPACITANCE

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6-4	AFN-00735C

Image 113

Intel MCS-80/85 manual Lc~

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.

Contents

Page Inter INTEl Corporation Table of Contents Page Introduction Page Chapter Part 1 Introduction to Functions of a Computer Instruction Register and Decoder Program Counter Jumps, Subroutines and the Stack Address Registers Control CircuitryArithmetic/Logic Unit ALU Timing Memory Read Instruction FetchMemory Write Wait memory synchronization Module Evolution MCS·SS Microcomputer System Introduction to MCS-85 Software Compatibility 8155 =CE, 8156 =CE MCS·S5 Special Peripheral Components ·1. MCS·SS Basic System MEMil. lOR Interfacing to MCS·80/8S Programmable Peripheral ComponentsProgrammable Peripherals Demultiplexing the BUS Interfacing to Standard Memory System Performance Instruction CYCLE/ACCESS TimeDistributed Processing Conclusions THROUGHPUT/COSTPage Functional Description Page Whatsin the 808SA ·1 808SA CPU Functional Block Diagram 122H Hexadecimalbinary A7HHexidecimal Binary AEH ·28085A Clock Logic ·38085A Hardware and SOFT· Ware RST Branch Locations ·5RIM Read Interrupt Mask ·4INTERRUPT Masks SET Using SIM Instruction Name Priority When Inter· Rupt occursType Branched to ·8BASIC CPU Functions HOW the MCS·85SYSTEM Works ·9 CPU Timing for Store Accumulator Direct STA Instruction Functional Description ·12808SA Machine State Chart ·13OPCODE Fetch Machine Cycle of DCX Instruction Lililili Memory Write MW Jl..Jl..Jl..J LIl..Jl..J ~ U- U-U V V U Lr \F LrLrU-U-U-U- U ~--r \J li\ Lr V V- U V u u u U ·21 Hold VS Interrupt NON Halt RST 5.5 Mask Resets SetsRST 6~5 Mask RST 7.5 Mask 7J==- 10ms.c = ~ ALE Signals Function AS-AI5 101M =x---C Conclusion Page System Operating Page LOA MvimSTA Lhld Address Assignment System Operation To , , I X X X Memory·Mapped ·-·-1 Dynamic RAM Interface Interfacing to MCS·80 PeripheralsInterfacing to Standard BUS Memories ·3 MCS·80 Peripherals with 110 Mapped Parts Functions Minimum MCS-85 System T1t Scale =11 System Operation ·8 Expanded System Parts Function System Operation Expanded MCS·85 SystemROM/EPROM CPUPage Functional Description Page Chapter 8080 Central Processor Unit Registers Data Bus Buffer Arithmetic and Logic Unit ALUInstruction Register and Control Machine Cycle Identification State Transition Sequence Status Bit Definitions $ no Irr\ RL- rL- rL.-h rL-h -h rL-rL- r-L State Associated Activities LnLn IrL Hold Sequences ~ ~ ~~ w---t. ~~u----t Wl ~ ~ Page Page Page Page Condition Iiii Instruction Set Page H,SP H,L000 B 011 E 100 H Instruction and Data Formats LabelData Word \JNN Condition Flags Addressing Modes Instruction SET Encyclopedia O o 1 1 o Instruction SET P,CY,AC XchgADD M R CY ~-1 ~-· 8085, 5 P,AC«H L 00 0 S S S DAA\ r Address,jng Cleared RLC ORA M 1 1 1 1 CMACMC Condition «SP Cycles 2/5 8085,315 States 9/18 8085, 11/17 Pop PchlFlag Word 1 0 16 8085, 18 RIM NOP SIM 8085A 8080Al8085A Instruction SET Index Sossa 808SA 808SA Instruction SET Summary Contd Device Specifications Page Inter Inter Absolute Maximum RATINGS· LC~ Wait Inter 8080Al8080A·1/8080A·2 Waveforms Data and Instruction Formats Instruction Set Summary Inter8080Al8080A·118080A·2 Inter8080A/8080A·1/8080A·2 8085AH Pin AH CPU Functional Block Diagram Configuration 8085AH/8085AH-2/8085AH-1 Vee Pin DescriptionInterrupt Priority, Restart Address, and Sensitivity Interrupt and Serial 1/0 Driving the X1 and X2 Inputs MHz Input Frequency External Clock Quartz Crystal Clock DriverDriver Circuit LC Tuned Circuit Clock Driver RiD~ 001 AH Basic System Timing AH Machine State Chart SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS· 8085AH/8085AH-2/8085AH-1 Characteristics 8085AH 8085AH-2 8085AH-1 Bus Timing Specification as a Teye Dependent Symbol TlDW 8085AH/8085AH-2/8085AH-1 Waveforms IntJ 8085AH/8085AH-2/8085AH-1 I8085AH/8085AH-2/8085AH-1 SA Pin CPU Functional Block Diagram = ov ±5%, Vss = OV unless otherwise specified Absolute Maximum Ratings ClK low Time Standard ClK loading TCYC ClK Cycle Period 320 2000120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising Xi Rising to ClK Falling 150 Ready Setup Time to leading Edge Symbol Parameter 8085A2 8085A·22 Units Min MaxTrailing Edge of Read to Re·Enabling Address TRD Read or Inta to Valid DataPage Appendix Page Appendix AP.PLICATIONS of MCS-85 Baud Rates MCS-85 Applications 111J RLm LlL R14 PAt8~~P Additional 808SA Interrupts 64K 16K 32KMemory Addressing As an example letslook at IntelsROM/EPROM family Fig Ihl YT~~ Static Memories EJ EJ EJ Refresh DMA Direct Memory AccessData D5H During initializationA4H LXI Sp =11 System Timings OT~ ·2Clock Related Timing Vs MHz Considerations 2T-80 Minimum System Memory Device Compatibility Address access TAD MEM Chip select access AddreS? access TAD MEM Chip select accessOutput enable TRD MEM BOSSA, A-2Memory Compatibility Bus Compatibility Analysis see Figure Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE Bus Compatibility Analysis see Contd TDHR 160 nsGates Flip Flops 15 ns 8216s 30 ns Flip flop 41 ns 200 10p,A Input Current TIL single load 40p,A 6mA Schottky or HtilTIL + 36 MOS Schotiky or 1 Htil Application Example 333 1 D1 Software Temperature Sensor Flow Diagram ~.,.-~ Thermistor Resistance Mapping JNZ search Has the entireReturn Clear HL CRT Interface RS·232C Interface Schematic Fi1 Output Routine HALFPrT PP-lPOP !? HO = + 6 =HOi 01H Bf?E Cassette Recorder Interface One Chip Magnetic Tape Interface Schematic BLl2 ButT01 ~1V! A..OCeH FeNO Bf1 JC TIl Additional Comments A1·43 Temperature Sensor Code Temperature Sensor Code Contd Temperature Sensor Code Contd Temperature Sensor Code Contd CRT and Cassette Code E81B ?EceBRm Ep! l 08,.1 ES77 C2760S 102 \/1ES7A Le? E87B C2760S 104 3E01 SEce06e9 RERn Eight Opta ens 0911 C2OC99 9914 C9TI2 TIl . Repeat Until Full BrTE ASSEt-18LEr Tu30B BlnIN a ,38 Eurcd a€18F2 089E BITSr ErTINBtl RRcrPage Workshops Page Experience Intel Workshops Chicago Area Boston AreaDallas Area SAN Francisco BAY Area Lab sessions on SDK-8S System Design Kit Introduction to Microprocessors MCS-80/85 Microprocessors Domestic Sales Offices IntJ ~9Jf69rt,~~9 \.,1 Inter Service Offices