intJ 8085AH/8085AH-2/8085AH-1

Table 6. Instruction Set Summary

 

I

 

 

Instruction Code

 

 

Operations

Mnemonic

D7 D6 Ds D4 D3 D2 D1 Do

 

Description

MOVE, LOAD, AND STORE

 

 

 

 

 

 

 

MOVr1 r2

 

 

0

1 D 0 0 S S S

Move register to register

MOVM.r

 

 

0 1 1 1 0

S

S

S

Move register to memory

 

 

MOVr.M

 

 

0

1

0

0

0

1

 

1

0

Move memory to register

 

 

 

MVI r

 

 

0

0 0 0 0 1 1 0

Move immediate register

MVIM

 

 

0

0 1 1 0 1 1 0

Move immediate memory

LXIB

 

 

0

0

0

0

0

0

 

0

1

Load immediate register

 

 

 

 

 

 

 

 

 

 

 

 

Pair B & C

LXID

 

 

0

0

0

1

0

0

 

0

1

Load immediate register

 

 

 

 

 

 

 

 

 

 

 

 

Pair 0 & E

LXIH

 

 

0

0

1

0

0

0

 

0

1

Load immediate register

STAX B

 

 

0

0

0

0

0

0

 

 

0

Pair H & L

 

 

 

 

 

 

 

1

Store A indirect

STAX D

 

 

0

0

0

1

0

0

 

1

0

Store A indirect

LDAXB

 

 

0

0 0 0 1 0

1 0

Load A indirect

LDAXD

 

 

0

0 0 1 1 0

1 0

Load A indirect

STA

 

 

0

0

1

1

0

0

 

1

0

Store A direct

LOA

 

 

0

0 1 1 1 0

1 0

Load A direct

SHLD

 

 

0

0 1 0 0 0

1 0

Store H & L direct

LHLD

 

 

0

0 1 0 1 0 1 0

Load H & L direct

XCHG

 

 

1

1

1

0

1

0

 

1

1

Exchange 0 & E, H & L

 

 

 

 

 

 

 

 

 

 

 

 

Registers

STACK OPS

 

 

 

 

0

0

0

1

0

 

Push register Pair B &

PUSH B

 

 

1

1

1

 

 

 

 

 

 

 

 

 

 

 

 

C on stack

PUSH 0

 

 

1

1

0

1

0

1

 

0

1

Push register Pair 0 &

 

 

 

 

 

 

 

 

 

 

 

 

E on stack

PUSH H

 

 

1

1

1

0

0

1

 

0

1

Push register Pair H &

 

 

 

 

 

 

 

0

 

 

0

 

L on stack

PUSH PSW

 

 

1

1

1

1

1

 

1

Push A and Flags

 

 

 

 

 

 

 

 

 

 

 

 

on stack

POP B

 

 

1 1

0

0

0

0

 

0

1

Pop register Pair B &

 

 

 

 

 

 

 

 

 

 

 

 

C off stack

POP D

 

 

1

1

0

1

0

0

 

0

1

Pep register Pair D &

 

 

 

 

 

 

 

 

 

 

 

 

E off stack

POP H

 

 

1 1

1

0

0

0

 

0

1

Pop register Pair H &

 

 

 

 

 

 

 

 

 

 

 

 

L off stack

POP PSW

 

 

1

1

1

1

0

0

 

0

1

Pop A and Flags

 

 

 

 

 

 

 

 

 

 

 

 

off stack

XTHL

 

 

1 1 1 0 0

0

 

1

1

Exchange top of

 

 

 

 

 

 

 

 

 

 

 

 

stack, H & L

SPHL

 

 

1 1 1 1 1 0 0 1

H & L to stack pointer

 

 

LXI SP

 

 

0

0

1

1

0

0

 

0

1

Load immediate stack

 

 

 

 

 

 

 

 

 

 

 

 

pointer

INX SP

 

 

0 0 1 1 0

0

 

1

1

Increment stack pointer

DCXSP

 

 

0

0

1

1

1

0

1

1

Decrement stack

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pointer

JUMP

 

 

1 1 0 0 0 0 1 1

 

 

JMP

 

 

Jump unconditional

JC

 

 

1 1 0 1 1 0 1 0

Jump on carry

JNC

 

 

1 1 0 1 0 0 1 0

Jump on no carry

JZ

 

 

1 1 0 0 1 0 1 0

Jump on zero

JNZ

 

 

1 1 0 0 0 0 1 0

Jump on no zero

JP

 

 

1 1 1 1 0 0 1 0

Jump on positive

JM

 

 

1 1 1 1 1 0 1 0

Jump on minus

JPE

 

 

1 1 1 0 1 0 1 0

Jump on parity even

JPO

 

 

1 1

1 0 0 0 1 0

Jump on parity odd

PCHL

 

 

1 1

1

0

1

0

0

1

H & L to program

 

 

 

 

 

 

 

 

 

 

 

 

counter

CALL

 

 

1 1 0 0 1 1 0 1

 

 

CALL

 

 

Cali unconditional

 

CC

 

1 1 0 1 1 1

0

0

Cali on carry

CNC

 

1 1

0

1

0

1

0

0

Cali on no carry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mnemonic

 

 

Instruction Code

 

 

Operations

 

D7 D6 Ds D4 D3 D2 D1

Do

Description

 

 

 

CZ

1 1 0 0 1 1 0

0

 

Cali on zero

 

CNZ

1

1

0

0

0 1 0

0

 

Cali on no zero

 

CP

1 1 1 1 0 1 0

0

 

Cali on positive

 

 

 

CM

1 1 1 1 1 1 0

0

 

Cali on minus

 

 

 

CPE

1

1

1 0

1 1 0

0

 

Cali on parity even

 

 

 

CPO

1

1

1 0

0 1 0

0

 

Cali on Daritv odd

 

 

 

RETURN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RET

1

1

0

0

1

 

0

0

1

 

Return

 

 

 

RC

1

1

0

1

1

 

0

0

0

 

Return on carry

 

 

 

RNC

1

1

0

1

0

 

0

0

0

 

Return on no carry

 

 

 

 

RZ

1

1

0

0

1

 

0

0

0

 

Return on zero

 

 

 

 

RNZ

1

1

0

0

0

 

0

0

0

 

Return on no zero

 

 

 

 

RP

1

1 1 1 0 0

0

0

 

Return on positive

 

 

 

 

RM

1

1 1 1 1 0

0

0

 

Return on minus

 

 

 

 

RPE

1

1

1

0

1 0

0

0

 

Return on parity even

 

 

 

 

RPO

1

1

1

0

0

 

0

0

0

 

Retu rn on parity odd

 

 

 

 

RESTART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RST

1

1 A A A 1 1

1

 

Restart

 

 

 

 

 

 

INPUT/OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

I~

1

0

1

1

 

0

1

1

 

Input

 

 

OUT

1

0

1

0

 

0

1

1

 

Output

 

 

 

 

INCREMENT AND DECREMENT

 

 

 

 

 

 

 

 

 

INR r

0 0 0 0 0 1 0

0

 

Increment register

 

 

OCR r

0

0

0 0 0 1 0

1

 

Decrement register

 

 

INR M

0

0

1 1 0 1 0

0

 

Increment memory

 

 

 

 

OCR M

0

0

1 1 0 1 0

1

 

Decrement memory

 

 

INX B

0

0

0

0

0

 

0

1

1

 

Increment B & C

 

 

 

 

 

 

 

 

 

 

 

 

 

registers

 

 

INX D

0

0

0

1

0

 

0

1

1

 

Increment 0 & E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

registers

 

 

INX H

0

0

1

0

0

 

0

1

1

 

Increment H & L

 

 

 

 

 

 

 

 

 

 

 

 

 

registers

 

 

DCX B

0

0

0

0

1

 

0

1

1

 

Decrement B & C

 

 

DCX D

0

0

0

1

1

 

0

1

1

 

Decrement D & E

 

 

DCX H

0

0

1

0

1

 

0

1

1

 

Decrement H & L

 

 

ADD

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

ADD r

1

 

S S

S

Add register to A

 

 

 

 

ADC r

1

0

0

0

1

 

S S

S

Add register to A

 

 

 

 

 

 

 

 

 

 

 

 

 

with carry

 

 

ADDM

1

0

C 0 0 1 1

0

 

Add memory to A

 

 

ADCM

1

0

0

0

1

 

1

1

0

 

Add memory to A

 

 

 

 

 

 

 

 

 

 

 

 

 

with carry

 

 

ADI

1

1

0

0

0

 

1

1

0

 

Add immediate to A

 

 

ACI

1

1

0

0

1

 

1

1

0

 

Add immediate to A

 

 

 

 

 

 

 

 

 

 

 

 

 

with carry

 

 

DAD B

0

0

0

0

1

 

0

0

1

 

Add B & C to H & L

 

 

DAD 0

0

0

0

1

1

 

0

0

1

 

Add 0 & E to H & L

 

 

DADH

0

0

1

0

1

 

0

0

1

 

Add H & L to H & L

 

 

 

 

DADSP

0

0

1

1

1

 

0

0

1

 

Add stack pointer to

 

 

 

 

 

 

 

 

 

 

 

 

 

H&L

 

 

SUBTRACT

 

0

0

 

0

 

 

 

 

 

 

 

 

 

 

SUB r

1

1

 

S S

S

Subtract register

 

 

 

 

 

 

 

 

 

 

 

 

 

from A

 

 

SBB r

1

0

0 1 1 S S

S

Subtract register from

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A with borrow

 

 

SUBM

1

0

0

1

0

 

1

1

0

 

Subtract memory

 

 

 

 

 

 

 

 

 

 

 

 

 

from A

 

 

SBBM

1

0

0

1

1

 

1

1

0

 

Subtract memory from

 

 

 

 

 

0

 

0

 

 

 

0

 

A with borrow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUI

1

1

1

 

1

1

 

Subtract immediate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from A

 

 

SBI

1

1

0

1

1

 

1 1

0

 

Subtract immediate

 

 

 

 

 

 

 

 

 

 

 

 

 

from A with borrow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6-24

AFN·0183SC

Page 133
Image 133
Intel MCS-80/85 manual IntJ 8085AH/8085AH-2/8085AH-1

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.