+6V

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

N.C. 2

 

 

 

 

 

 

 

 

SID

 

6

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

13

 

 

 

 

 

 

 

 

 

MCI489

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

"::"

 

 

 

 

 

 

 

 

 

 

+12V

 

-12V

 

 

 

 

8086

 

 

 

 

 

 

 

 

 

 

 

 

SOD

 

4

 

 

 

 

 

 

330pF

 

 

 

 

 

 

 

 

 

 

 

 

10

...----....__

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

121--.....----...

 

 

 

 

 

 

 

 

 

13...----....__

 

 

 

 

 

 

 

 

 

 

 

MCI488

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GNDr~~------------~--------~--~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jl

CRT DATA OUT

CRT DATA IN

SIGNAL

GROUND

0

o 0 0 0 000 0 0 0 00000000 0

0<0

Figure 23. RS·232C Interface Schematic

Upon power-up or reset, or when the console device baud rate is changed, the baud rate identifi- cation subroutine (BRIO) is called. This routine waits until an ASCII space character (20H) is received from the console. (Any other character will result in a case of mistaken identification.) When a space character is received, two time parameters are computed which correspond to the bit time and one-half the bit time of the baud rate being used. These are stored as variables BITTIME and HALFBIT. To output a character to the con- sole, the character code is placed in register C, and the subroutine COUT is called. This routine uses BITTIME as a parameter for the software delay loop which determines the baud rate. To accept r. character from the keyboard, CIN is called. CI1\I returns after the next key is typed, with the corre- sponding character code in register C. CIN uses both parameters BITTIME and HALFBIT.

Since COUT and CIN use time parameters com- puted by BRIO, they will function at a rate the same as that of the initial space character input. Because of the nature of the software, the rate does not depend on the CPU clock frequency. This

results in additional flexibility in the following respects:

1.The software does not need to be modified if the 8085 crystal frequency is changed or Wait states are added.

2.Since the time base is no longer critical, the quartz crystal could be replaced by a less expensive RC network, provided the fre- quency does not drift by more than a few percent during a session. Additional drift can be accommodated by periodically recalling the BRIO routine.

3.Communication is possible at non-standard baud rates which relaxes the constraints on system peripherals.

It should be noted, though, that slowing down the CPU clock will decrease its throughput proportion- ately. In addition, it will degrade the maximum resolution of the delay loops, with the result that the highest baud rates may no longer be achievable.

A more detailed analysis of the CRT interface routines will be presented in the order of increasing complexity: COUT, CIN, and BRIO. Since SIO and

A1-33

Page 173 Page 175
Page 174
Image 174
Intel MCS-80/85 manual RS·232C Interface Schematic
Page 173 Page 175

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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